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2019-03-26mem: Deleting this init() method was accidentally dropped during rebase.Gabe Black
Deleting this init() method was part of a change just committed, but was accidentally dropped during a rebase. Change-Id: I0f22778596ed11e182f3111d9999a0fef727f6cc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17688 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-26mem: Clean up the xbars a little.Gabe Black
Get rid of comments which just restate the code, get rid of redundant "virtual" keywords, add "override"s, fix style, and get rid of xbar::init which was empty and hiding the parent class init. Change-Id: I8ce20abee340baa88084d142f2fb8c633ee54ba9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17592 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-23misc: missing override specifierAndrea Mondelli
Missing specifier of overridden virtual function declared in sim_object.hh Removed redundant "virtual" keyword Change-Id: I42aa3349b537c9e62607bce20cf1b3aabdb99bf2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17468 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-20mem-cache: Added the STeMS prefetcherJavier Bueno
Reference: Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, and Babak Falsafi. 2009. Spatio-temporal memory streaming. In Proceedings of the 36th annual international symposium on Computer architecture (ISCA '09). ACM, New York, NY, USA, 69-80. Change-Id: I58cea1a7faa9391f8aa4469eb4973feabd31097a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16423 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary. Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-19mem: Move bind() and unbind() into the Port class.Gabe Black
These are now pure virtual methods which more specialized port subclasses will need to implement. The SlavePort class implements them by ignoring them and then providing parallel functions for the MasterPort to call. The MasterPort's methods do basically what they did before, except now bind() uses dynamic cast to check if its peer is of the appropriate type and also to convert it into that type before connecting to it. Change-Id: I0948799bc954acaebf371e6b6612cee1d3023bc4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17038 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-18mem-cache: tautological comparison of byteOrderAndrea Mondelli
Error: build/X86/mem/cache/prefetch/indirect_memory.cc:56:24: error: result of comparison of constant -1 with expression of type 'const ByteOrder' is always false [-Werror,-Wtautological-constant-out-of-range-compare] fatal_if(byteOrder == -1, "This prefetcher requires a defined ISA\n"); ~~~~~~~~~ ^ ~~ build/X86/base/logging.hh:205:14: note: expanded from macro 'fatal_if' if ((cond)) { \ ^~~~ 1 error generated. Fix: cast of constant (-1) used in comparison Change-Id: I3deb154c2fe5b92c4ddf499176cb185c4ec7cf64 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17388 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-15mem: Removed circular include refRyan Gambord
If BasicLink.hh is modified, the style checker forces a reordering of the includes, which results in build errors because it ends up including Topology.hh before including its xxxParams.hh files, which include forward declarations of the BasicLink family of classes, and so Topology.hh throws errors that BasicLink etc. are not declared. Change-Id: I664a0652e53f0cc61763c2190a980c655b85d397 Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17270 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-15mem-cache: Added the Indirect Memory PrefetcherJavier Bueno
Reference: Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, and Srinivas Devadas. 2015. IMP: indirect memory prefetcher. In Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48). ACM, New York, NY, USA, 178-190. DOI: https://doi.org/10.1145/2830772.2830807 Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16223 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-15mem: Move the Port base class into sim.Gabe Black
The Port class is going to be officially used for more than just memory system connections. Change-Id: I493e721f99051865c5f0c06946a2303ff723c2af Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17036 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-15mem: Track the MemObject owner in MasterPort and SlavePort.Gabe Black
These types are much more tied to MemObjects and the gem5 memory protocol than the Port or BaseMasterPort and BaseSlavePort classes. Change-Id: I36bc8c75b9c74d28ee8b65dbcbf742cd41135742 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17032 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-15mem-cache: Fix write hit latency calculation orderDaniel
Patch 6d8694a5fb5cfb905186249581cc6a3fde6cc38a changes the order at which the access latency is calculated for hits. This order is incorrect, since the calculations must use the blk's whenReady value before the access is satisfied. Change-Id: I30dae5435f54200cc8fdf71fd0dbd2cf9c6f8b17 Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17190 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-12mem-cache: Removed default arg from get() in prefetch/base.hhRyan Gambord
commit b0d1643 caused building against NULL to break due to NULLIsa::GuestByteOrder not being defined. Removal of default argument in src/mem/cache/prefetch/base.hh fixes this. Change-Id: I99a4abb4be1418fadec145481164f7caa3334ca0 Signed-off-by: Ryan Gambord Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17070 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-11mem-cache: Revert "mem-cache: Remove Packet dependency in Tags"Daniel R. Carvalho
Reverting patch due to polymorphism limitations. This reverts commit 86a54d91936b524c0ef0f282959f0fc29bafe7eb. Change-Id: Ie032dcc5176448c62118c89732b3cc6b8efd5a13 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17049 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-10mem-cache: Added extra information to PrefetchInfoJavier Bueno
Added additional information to the PrefetchInfo data structure - Whether the event is triggered by a cache miss - Whether the event is a write or a read - Size of the data accessed - Data accessed by the request Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16583 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-07mem-cache: Add header delay to handleFill whenReadyDaniel R. Carvalho
A prefetch response will have a header delay, which was not being taken into account. Change-Id: I66a071bc81ef41b8c0de37aa2df75171d1979a6f Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14895 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-07mem-cache: Allow tag-only accesses on latency calculationDaniel R. Carvalho
Some accesses only need to search for a tag in the tag array, with no need to touch the data array. This is the case for CleanEvicts, evicts that don't find a corresponding block entry (since a write cannot be done in parallel with tag lookup), and maintenance operations. Change-Id: I7365a915500b5d7ab636d49a9acc627072a7f58e Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14878 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-07mem-cache: Add lookup latency to access' whenReadyDaniel R. Carvalho
When dealing with writebacks, as soon as the packet metadata arrives there will be a tag lookup, done sequentially because a write can't be done in parallel. While the tag lookup is being done, the payload will arrive. When both the payload are present and the tag is correct block entry is determined the fill happens. Change-Id: If1a0085d742458b675bfc012b6d908d9d9a25e32 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14877 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-07mem-cache: Fix recvTimingReq doWritebacks tickDaniel R. Carvalho
Before being sent to the writebuffer, the evicted blocks must be selected for replacement, and therefore the access latency must be applied. The forward latency is then applied on top of that delay. Change-Id: I16a25a8bf6051f63eb7a02fe66acb6af26d434fc Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14736 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-07mem-cache: Use header delay on latency calculationDaniel R. Carvalho
Previously the bus delay was being ignored for the access latency calculation, and then applied on top of the access latency. This patch fixes the order, as first the packet must arrive before the access starts. Change-Id: I6d55299a911d54625c147814dd423bfc63ef1b65 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14876 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-03-07mem-cache: Remove old todo about latency in hit functionDaniel R. Carvalho
The header and payload delay have already been accounted and zeroed previous to calling this function. The probe is not allowed to modify the packet, therefore no extra delays are added, and it is safe to remove the todo note. Change-Id: I8ddf7e189fbe609cdec34364f3c013427930daf7 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14875 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-02-28ruby: Fix garnet's round robin arbitration for vc selectionSrikant Bharadwaj
Garnet utilizes round robin policy to select a VC for transmission ar Network Interface and Routers. The current logic for round robin is only fair if all the virtual networks are active at a given router. If the router or network interface is not receiving traffic in from any vnet then the priority is always taken up by the next vnet in numerically (or loops back to 0). This fix changes the way we perform round robin arbitration. When a VC is selected in a cycle, the round robin pointer is set to the VC next to it and is iterated from there on. If any VC does not have a flit in a given cycle, it will lose its turn until the next round. At maximum traffic this will model round robin correctly even if a certain VNET is not active at that unit. Change-Id: I9bf805221054f9f25bee14b57ff521f4ce4ca980 Reviewed-on: https://gem5-review.googlesource.com/c/16688 Reviewed-by: Jieming Yin <Jieming.Yin@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-28mem-cache: Sandbox Based Optimal Offset ImplementationIvan Pizarro
Brown, N. T., & Sendag, R. Sandbox Based Optimal Offset Estimation. Change-Id: Ieb693b6b2c3d8bdfb6948389ca10e92c85454862 Reviewed-on: https://gem5-review.googlesource.com/c/15095 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-02-26mem-cache: Copy over flags to forwarded responseNikos Nikoleris
A cache that forwards a request to the memory below does not fill and forwards the response with the data to cache above. This change ensures that the flags of the original response are also preserved. Change-Id: I244b20b073c31b976358816c5b14bba413b8271f Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16182 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2019-02-25mem-cache: added missing override specifier in BoPAndrea Mondelli
Added missing specifier for various virtual functions. Change-Id: I41aebb3b76bce6dd3bee21ac0e2b0e52cb90fc80 Reviewed-on: https://gem5-review.googlesource.com/c/16728 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-02-25python: Stop using basestring to test for stringsAndreas Sandberg
The base class basestring doesn't exist in Python 3. Use string_types from six instead. Change-Id: I7e84903fb7dd4a0af7ae4e9f4ec2e54338f212bb Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15998 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com>
2019-02-25mem-cache: A Best-Offset PrefetcherIvan Pizarro
Michaud, P. (2015, June). A best-offset prefetcher. In 2nd Data Prefetching Championship. Change-Id: I61bb89ca5639356d54aeb04e856d5bf6e8805c22 Reviewed-on: https://gem5-review.googlesource.com/c/14820 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-02-22python: Make iterator handling Python 3 compatibleAndreas Sandberg
Many functions that used to return lists (e.g., dict.items()) now return iterators and their iterator counterparts (e.g., dict.iteritems()) have been removed. Switch calls to the Python 2.7 iterator methods to use the Python 3 equivalent and add explicit list conversions where necessary. Change-Id: I0c18114955af8f4932d81fb689a0adb939dafaba Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15992 Reviewed-by: Juha Jäykkä <juha.jaykka@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-02-22mem-cache: Add a mechanism to iterate all entries of an AssociativeSetJavier Bueno
Added functions to obtain an iterator to access all entries of an AssociativeSet container. Change-Id: I1ec555bd97d97e3edaced2b8f61287e922279c26 Reviewed-on: https://gem5-review.googlesource.com/c/16582 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-02-21mem-cache: Added the Slim AMPM PrefetcherJavier Bueno
Reference: Towards Bandwidth-Efficient Prefetching with Slim AMPM. Young, V., & Krishna, A. (2015). The 2nd Data Prefetching Championship. Slim AMPM is composed of two prefetchers, the DPCT and the AMPM (both already in gem5). Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a Reviewed-on: https://gem5-review.googlesource.com/c/16383 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-02-12python: Replace dict.has_key with 'key in dict'Andreas Sandberg
Python 3 has removed dict.has_key in favour of 'key in dict'. Change-Id: I9852a5f57d672bea815308eb647a0ce45624fad5 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15987 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-12python: Replace orderdict with collections.OrderedDictAndreas Sandberg
Python 2.7 and newer has support for ordered dictionaries in the standard library. Remove this custom class. Change-Id: I4b720405aa3c4ce8d5c0b401eefe744a85ac3a3e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16362 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-02-12mem-cache: Irregular Stream Buffer PrefetcherJavier Bueno
Based in the description of the following publication: Akanksha Jain and Calvin Lin. 2013. Linearizing irregular memory accesses for improved correlated prefetching. In Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM, New York, NY, USA, 247-259. Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165 Reviewed-on: https://gem5-review.googlesource.com/c/15215 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2019-02-12mem-cache: Added the Delta Correlating Prediction Tables PrefetcherJavier Bueno
Reference: Multi-level hardware prefetching using low complexity delta correlating prediction tables with partial matching. Marius Grannaes, Magnus Jahre, and Lasse Natvig. 2010. In Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers (HiPEAC'10) Change-Id: I7b5d7ede9284862a427cfd5693a47652a69ed49d Reviewed-on: https://gem5-review.googlesource.com/c/16062 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
The importer in Python 3 doesn't like the way we import SimObjects from the global namespace. Convert the existing SimObject declarations to import from m5.objects. As a side-effect, this makes these files consistent with configuration files. Change-Id: I11153502b430822130722839e1fa767b82a027aa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15981 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-12mem-ruby: Fixing TopologyPouya Fotouhi
The constructor assumes the number of nodes (i.e. controllers) equal to the number of external nodes. This is a not necessarily valid for all cases (e.g MESI_Three_Level - where L0s are directly connected to L1s). MachineType_base_number(MachineType_NUM) provides the total number of controllers. Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Change-Id: Id906099dc967ec70aa34dedb0b55351031ff242c Reviewed-on: https://gem5-review.googlesource.com/c/15716 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-12mem-ruby: Fixing MESI Three LevelPouya Fotouhi
Adding back some changes done in patch 676ae57827. Transient state IS_I, STALE_DATA, Data_Stale event are necessary. Issue: (cacheline A, initial state for P0 and P1 is I) | P0 | P1 | |GETX (A)| | | |GETS (A)| |Inv_All | | P1 never sends the ACK - deadlock It should ACK, later upon data use it as stale data, and got to I. Solution: P1(A): GETS: I->IS Inv_All: IS->IS_I, Send ACK Data: IS_I->I, STALE_DATA to L0 Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Change-Id: I1e7b2c05439d08579c68d8eb444e0f332e75e07f Reviewed-on: https://gem5-review.googlesource.com/c/15715 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-01mem-cache: Updated version of the Signature Path PrefetcherJavier Bueno
This implementation is based in the description available in: Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy, Chris Wilkerson, and Zeshan Chishti. 2016. Path confidence based lookahead prefetching. In The 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-49). IEEE Press, Piscataway, NJ, USA, Article 60, 12 pages. Change-Id: I4b8b54efef48ced7044bd535de9a69bca68d47d9 Reviewed-on: https://gem5-review.googlesource.com/c/14819 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-01-23mem-ruby: Fix missing TBE allocation and deallocationZicong Wang
The TBE allocation and deallcation are currently missing during the directory state transition from I to M in protocol MI_example. Change-Id: If7569c02faf56ea84c34ee1345f1a33d318cdfff Signed-off-by: Zicong Wang <wangzicong@nudt.edu.cn> Reviewed-on: https://gem5-review.googlesource.com/c/15535 Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-22mem: Add tryTiming suppport to CommMonitorSascha Bischoff
The CommMonitor did not support tryTiming, which resulted in gem5 panicing if the CommMonitor was used. With this change, we update the CommMonitor pass through the tryTiming() calls. Change-Id: I86810170e5e10a0c5d63af76fc4a6ab70710d2fb Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15736 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-17mem: Allow inserts in the begining of a packet queueNikos Nikoleris
A packet queue keeps track of packets that are scheduled to be sent at a specified time. Packets are sorted such that the packet with the earliest scheduled time is at the front of the list (unless there are other ordering requirements). Previouly, the implemented algorithm didn't allow packets to be placed at the front of the queue resulting in uneccessary delays. This change fixes the implementation of schedSendTiming. Change-Id: Ic74abec7c3f4c12dbf67b5ab26a8d4232e18e19e Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15556 Reviewed-by: Bradley Wang <radwang@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-17mem: Determine if a packet queue forces ordering at constructionNikos Nikoleris
A packet queue is typically used to hold on to packets that are schedules to be sent in the future or when they need to queue behind younger packets that have been sent out yet. Due to memory order requirements, some MemObjects need to maintain the order for packet (mostly responses) that reference the same cache block. Prior to this patch the ordering requirements where determined when the packet was scheduled to be sent. This patch moves the parameter to the constructor. Change-Id: Ieb4d94e86bc7514f5036b313ec23ea47dd653164 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15555 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-01-16mem-cache: Access Map Pattern Matching PrefetcherJavier Bueno
Implementation of the Access Map Pattern Matching prefetcher Based in the description of the following paper: Access map pattern matching for high performance data cache prefetch. Ishii, Y., Inaba, M., & Hiraki, K. (2011). Journal of Instruction-Level Parallelism, 13, 1-24. Change-Id: I0d4b7f7afc2ab4938bdd8755bfed26e26a28530c Reviewed-on: https://gem5-review.googlesource.com/c/15096 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-01-16mem-cache: Signature Path PrefetcherJavier Bueno
Related paper: Lookahead Prefetching with Signature Path J Kim, PV Gratz, ALN Reddy The 2nd Data Prefetching Championship (DPC2), 2015 Change-Id: I2319be2fa409f955f65e1bf1e1bb2d6d9a4fea11 Reviewed-on: https://gem5-review.googlesource.com/c/14737 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-01-16mem-cache: allow prefetchers to emit page crossing referencesJavier Bueno
QueuedPrefetcher takes the responsability to check for page crossing references. Change-Id: I0ae6bf8be465118990d9ea1cac0da8f70e69aeb1 Reviewed-on: https://gem5-review.googlesource.com/c/14735 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-01-16mem-cache: virtual address support for prefetchersJavier Bueno
Prefetchers can be configured to operate with virtual or physical addreses. The option can be configured through the "use_virtual_addresses" parameter of the Prefetcher object. Change-Id: I4f8c3687988afecc8a91c3c5b2d44cc0580f72aa Reviewed-on: https://gem5-review.googlesource.com/c/14416 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-12-07mem: Compile tracePacket only when TRACING_ON is definedGiacomo Travaglini
If TRACING_ON is not defined (e.g. when building gem5.fast), clang compilations will fail reporting an unused function. Change-Id: I959dba6e9fcf74b951e16365077939ae4d4ef924 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14975 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-12-07mem-cache: Workaround for setWhenReady assertionDaniel R. Carvalho
Change 174da8e2da6a896d2e97bc264f9c827a0f4c35ac added an assert that is not satisfiable with current implementation, breaking some regression tests. Change-Id: Ibafaf0c51906384364f0b2a4b931f8ec6126d858 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14955 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-12-05mem-cache: Remove writebacks parameter from serviceMSHRTargetsDaniel R. Carvalho
Change 8ba77ae8fc98a355082da2bd9fdc6ecf4928f725 introduced the writebacks parameter, but it was never used. Change-Id: I225e5b399de42d77c72fc0012d3dc93ef39b8853 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14896 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-12-04mem-cache: Add getter and setter to CacheBlk::whenReadyDaniel R. Carvalho
Add a getter and a setter function to access CacheBlk::whenReady to encapsulate the variable and allow error checking. This error checking consists on verifying that writes to a block after it has been inserted follow a chronological order. As a side effect, tickInserted retain its value until updated, that is, it is not reset in invalidate(). Change-Id: Idc3c5a99c3f002ee9acc2424f00e554877fd3a69 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14715 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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