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2010-09-12swig: make all generated files go into the m5.internal packageNathan Binkert
This is necessary because versions of swig older than 1.3.39 fail to do the right thing and try to do relative imports for everything (even with the package= option to %module). Instead of putting params in the m5.internal.params package, put params in the m5.internal package and make all param modules start with param_. Same thing for m5.internal.enums. Also, stop importing all generated params into m5.objects. They are not necessary and now with everything using relative imports we wound up with pollution of the namespace (where builtin-range got overridden). --HG-- rename : src/python/m5/internal/enums/__init__.py => src/python/m5/internal/enums.py rename : src/python/m5/internal/params/__init__.py => src/python/m5/internal/params.py
2010-09-09scons: Stop building the big monolithic swigged params moduleNathan Binkert
kill params.i and create a separate .i for each object (param, enums, etc.)
2010-09-09init: don't build files that centralize python and swig codeNathan Binkert
Instead of putting all object files into m5/object/__init__.py, interrogate the importer to find out what should be imported. Instead of creating a single file that lists all of the embedded python modules, use static object construction to put those objects onto a list. Do something similar for embedded swig (C++) code.
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. --HG-- rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py rename : src/python/m5/objects/Device.py => src/dev/Device.py rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py rename : src/python/m5/objects/Ide.py => src/dev/Ide.py rename : src/python/m5/objects/Pci.py => src/dev/Pci.py rename : src/python/m5/objects/Platform.py => src/dev/Platform.py rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py rename : src/python/m5/objects/Uart.py => src/dev/Uart.py rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py rename : src/python/m5/objects/Bus.py => src/mem/Bus.py rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py rename : src/python/m5/objects/Process.py => src/sim/Process.py rename : src/python/m5/objects/Root.py => src/sim/Root.py rename : src/python/m5/objects/System.py => src/sim/System.py extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
2007-05-19PhysicalMemory has vector of uniform ports instead of one special one.Steve Reinhardt
configs/example/memtest.py: PhysicalMemory has vector of uniform ports instead of one special one. Other updates to fix obsolete brokenness. src/mem/physical.cc: src/mem/physical.hh: src/python/m5/objects/PhysicalMemory.py: Have vector of uniform ports instead of one special one. src/python/swig/pyobject.cc: Add comment. --HG-- extra : convert_revision : a4a764dcdcd9720bcd07c979d0ece311fc8cb4f1
2007-05-10remove hit_latency and make latency do the right thingAli Saidi
set the latency parameter in terms of a latency add caches to tsunami-simple configs configs/common/Caches.py: tests/configs/memtest.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: set the latency parameter in terms of a latency configs/common/FSConfig.py: give the bridge a default latency too src/mem/cache/cache_builder.cc: src/python/m5/objects/BaseCache.py: remove hit_latency and make latency do the right thing tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: add caches to tsunami-simple configs --HG-- extra : convert_revision : 37bef7c652e97c8cdb91f471fba62978f89019f1
2007-05-10add/update parameters for bus bridgeAli Saidi
--HG-- extra : convert_revision : 063f757fbfa2c613328ffa70e556f8926623fa91
2007-05-07fix partial writes with a functional memory hackAli Saidi
figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached configs/common/FSConfig.py: src/mem/bridge.cc: src/mem/bridge.hh: src/python/m5/objects/Bridge.py: fix partial writes with a functional memory hack src/mem/bus.cc: src/mem/bus.hh: src/python/m5/objects/Bus.py: figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached src/mem/packet.cc: fix WriteInvalidateResp to not be a request that needs a response since it isn't src/mem/port.hh: by default return 0 for deviceBlockSize instead of panicing. This makes finding the block size the bus should use easier --HG-- extra : convert_revision : 3fcfe95f9f392ef76f324ee8bd1d7f6de95c1a64
2007-03-29Override addPrivateSplitL1Caches function in order to automatically set the ↵Kevin Lim
tgts_per_mshr of the caches to 20. This is needed otherwise things will potentially lock up when using the O3CPU because the caches can run out of targets, and then not respond. Remove this hack once the caches eventually get fixed. --HG-- extra : convert_revision : 8c61ac1b6182f57ebbe3bcfeddb5a4f4334d7bc0
2007-03-26first bit of life from the intel gigabit modelAli Saidi
--HG-- extra : convert_revision : d8944a53f6b585df21651c4e624518d5c49a7837
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. --HG-- extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
2007-03-03Add Iob and remove the fake deviceAli Saidi
configs/common/FSConfig.py: add an attachOnChipIO to force people to think about where "onchip" i/o should be connected in their hierarchy --HG-- extra : convert_revision : cf79a9a00760b7daf28063f407a04bd38b956843
2007-03-03Implement Niagara I/O interface and rework interruptsAli Saidi
configs/common/FSConfig.py: Use binaries we've compiled instead of the ones that come with Legion src/arch/alpha/interrupts.hh: get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number src/arch/sparc/asi.cc: Add AsiIsInterrupt() to AsiIsMmu() src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Add InterruptVector type src/arch/sparc/interrupts.hh: rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared src/arch/sparc/isa_traits.hh: Add the "interrupt" trap types to isa traits src/arch/sparc/miscregfile.cc: add names for all the misc registers and possible post an interrupt when TL is changed. src/arch/sparc/miscregfile.hh: Add a helper function to post an interrupt when pil < some set softint src/arch/sparc/regfile.cc: src/arch/sparc/regfile.hh: InterruptLevel shouldn't really live here, moved to interrupt.hh src/arch/sparc/tlb.cc: Add interrupt ASIs to TLB src/arch/sparc/ua2005.cc: Add checkSoftInt to check if a softint needs to be posted Check that a tickCompare isn't scheduled before scheduling one Post and clear interrupts on queue writes and what not src/base/bitfield.hh: Add an helper function to return the msb that is set src/cpu/base.cc: src/cpu/base.hh: get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending src/cpu/intr_control.cc: src/cpu/intr_control.hh: src/dev/alpha/tsunami_cchip.cc: src/python/m5/objects/IntrControl.py: Make IntrControl have a system pointer rather than using a cpu pointer to get one src/dev/sparc/SConscript: add iob to SConsscrip tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: update config.ini/out for intrcntrl not having a cpu pointer anymore --HG-- extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
2007-02-21Get rid of the ConsoleListener SimObject and just fold theNathan Binkert
relevant code directly into the SimConsole object. Now, you can easily turn off the listen port by just specifying 0 as the port. --HG-- extra : convert_revision : c8937fa45b429d8a0728e6c720a599e38972aaf0
2007-02-18Get rid of the Serialize and IntervalStats Param contextsNathan Binkert
since they're no longer used --HG-- extra : convert_revision : e39590aa03cc4c961d2eb5dab57862811f431e4d
2007-02-17Get rid of the Statistics and Statreset ParamContexts, andNathan Binkert
expose all of the relevant functionality to python. Clean up the mysql code while we're at it. --HG-- extra : convert_revision : 5b711202a5a452b8875ebefb136a156b65c24279
2007-02-13Make mulitple consoles work and be distinguishable from each otherAli Saidi
src/dev/alpha/tsunamireg.h: get rid of things that aren't really tsunami registers src/dev/platform.hh: src/dev/uart.cc: the uart pointer isn't used anymore src/dev/simconsole.cc: make the simconsole print something more useful to distinguish between various consoles in a single system src/dev/uart8250.hh: put the needed uart defines in here rather than including them from tsunamireg src/python/m5/objects/T1000.py: add a console to the T1000 config for the hypervisor --HG-- extra : convert_revision : 76ca92122e611eaf76b989bc699582eef8297be8
2007-02-13Merge all of the execution trace configuration stuff intoNathan Binkert
the traceflags infrastructure. InstExec is now just Exec and all of the command line options are now trace options. --HG-- extra : convert_revision : 4adfa9dfbb32622d30ef4e63c06c7d87da793c8f
2007-02-09Get rid of the Trace ParamContext and give python directNathan Binkert
access to enabling/disabling tracing. Command line is unchanged except for the removal of --trace-cycle since it's not so clear what that means. --HG-- extra : convert_revision : c0164d92d3615d76d0c6acaabaafd92a9278212a
2007-01-31make sparc fs less chattyAli Saidi
src/SConscript: strip doesn't take a src and dest in solaris --HG-- extra : convert_revision : 57f95eda0e3232475a5b55753ace3f3f0fced8b3
2007-01-25Move time forward to Jan 1, 2009 and update statsNathan Binkert
--HG-- extra : convert_revision : 9398362237443dc659f423a342bd27c923e90aea
2007-01-25Instead of passing an int to represent time between python and C++Nathan Binkert
pass the tuple of python's struct_time and interpret that. Fixes a problem where the local timezone leaked into the time calculation. Also fix things so that the unix, python, and RTC data sheets all get the right time. Provide both years since 1900 and BCD two digit year. Put the date back at 1/1/2006 for now. --HG-- extra : convert_revision : 473244572f468de2cb579a3dd7ae296a6f81f5d7
2007-01-21add dumb time of day deviceAli Saidi
--HG-- extra : convert_revision : 52e51ff49f7ed73065f04707ded06dc7254292c4
2007-01-09add memory mapped disk deviceAli Saidi
configs/common/FSConfig.py: src/python/m5/objects/T1000.py: add configuration for memory mapped disk src/dev/sparc/SConscript: add memory mapped disk to sconscript --HG-- extra : convert_revision : d8df4a455cf48000042d0ff93a274985f4dbe905
2007-01-03Add 'Time' as a parameter type that can accept variousNathan Binkert
formats for time (strings, datetime objects, etc.) Advance system time to 1/1/2009 Clean up time management code a little bit --HG-- extra : convert_revision : 28ebecc7ea6b12f4345c77a9a6b4bdf2e752c4f8
2006-12-29Merge zizzer.eecs.umich.edu:/bk/newmemNathan Binkert
into iceaxe.:/Volumes/work/m5/incoming --HG-- extra : convert_revision : dad5311afaaf40c1378017514c8b3f73852f13f5
2006-12-29FormattingNathan Binkert
--HG-- extra : convert_revision : f5a940a8b9aaba0703781b398cf29be581907c21
2006-12-27Bug fixes in the TLBAli Saidi
Make our replacement algorithm same as legion (although not same as the spec) itb should be 64 entries not 48 src/arch/sparc/tlb.cc: Bug fixes in the TLB Make our replacement algorithm same as legion (although not same as the spec) src/arch/sparc/tlb.hh: Make our replacement algorithm same as legion (although not same as the spec) src/python/m5/objects/SparcTLB.py: itb should be 64 entries too --HG-- extra : convert_revision : 1b5cb3597091e3cfe293e94f6f2219b1e621c35f
2006-12-15small change to eliminate address range overlap.Lisa Hsu
--HG-- extra : convert_revision : c8309a8774265a707c87c4f516bec1f81aff4a79
2006-12-12Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 --HG-- extra : convert_revision : 6e58629b1e51f1fc493a89f16c3f2e676dc5d191
2006-12-07get legion/m5 to first tlb miss faultAli Saidi
src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: add sparc error asi src/arch/sparc/faults.cc: put a panic in if TL == MaxTL src/arch/sparc/isa/decoder.isa: Hpstate needs to be updated on a done too src/arch/sparc/miscregfile.cc: warn istead of panicing of fprs/fsr accesses src/arch/sparc/tlb.cc: add sparc error register code that just does nothing fix a couple of other tlb bugs src/arch/sparc/ua2005.cc: fix implementation of HPSTATE write src/cpu/exetrace.cc: let exectrate mess up a couple of times before dying src/python/m5/objects/T1000.py: add l2 error status register fake devices --HG-- extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca
2006-12-04More changes to get SPARC fs closer. Now at 1.2M cycles before differenceAli Saidi
configs/common/FSConfig.py: seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config. src/arch/sparc/isa/decoder.isa: change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect src/arch/sparc/miscregfile.cc: For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this). Use instruction count from cpu rather than cycles because that is what legion does we can change it back after were done with legion src/base/bitfield.hh: add a new function mbits() that just masks off bits of interest but doesn't shift src/cpu/base.cc: src/cpu/base.hh: add instruction count to cpu src/cpu/exetrace.cc: src/cpu/m5legion_interface.h: compare instruction count between legion and m5 too src/cpu/simple/atomic.cc: change asserts of packet success to if panics wrapped with NDEBUG defines so we can get some more useful information when we have a bad address src/dev/isa_fake.cc: src/dev/isa_fake.hh: src/python/m5/objects/Device.py: expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses src/python/m5/objects/System.py: convert some tabs to spaces src/python/m5/objects/T1000.py: add more fake devices for each l1 bank and each memory controller --HG-- extra : convert_revision : 8024ae07b765a04ff6f600e5875b55d8a7d3d276
2006-12-02Fix help strings on GenRepl params.Steve Reinhardt
--HG-- extra : convert_revision : 520814e193b9e86b6410f3ab98d62ed131d295aa
2006-11-30Load the hypervisor symbols twice, once with an address mask so that we can ↵Ali Saidi
get symbols for where it's copied to in memory Add the ability to use an address mask for symbol loading Rather then silently failing on platform accesses panic Move BadAddr/IsaFake no Device from Tsunami Let the system kernel be none, but warn about it configs/common/FSConfig.py: We don't have a kernel for sparc yet src/arch/sparc/system.cc: Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory src/base/loader/aout_object.cc: src/base/loader/aout_object.hh: src/base/loader/ecoff_object.cc: src/base/loader/ecoff_object.hh: src/base/loader/elf_object.cc: src/base/loader/elf_object.hh: src/base/loader/object_file.hh: src/base/loader/raw_object.cc: src/base/loader/raw_object.hh: Add the ability to use an address mask for symbol loading src/dev/sparc/t1000.cc: Rather then silently failing on platform accesses panic src/dev/sparc/t1000.hh: fix up a couple of platform comments src/python/m5/objects/Bus.py: src/python/m5/objects/Device.py: src/python/m5/objects/T1000.py: src/python/m5/objects/Tsunami.py: Move BadAddr/IsaFake no Device from Tsunami src/python/m5/objects/System.py: Let kernel be none src/sim/system.cc: Let the system kernel be none, but warn about it --HG-- extra : convert_revision : 92f6afef599a3d3c7c5026d03434102c41c7b5f4
2006-11-22Added a parameter to set memory to zero. This is to support Legion, and once ↵Gabe Black
we can make our own hypervisor binary, we probably won't need it. --HG-- extra : convert_revision : 168883e4a5d3760962cd9759a6f41c66f5a6402a
2006-11-22Merge zizzer:/bk/sparcfsGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 75f3398e38e18eb1f8248e23708d7a8d8cce0fc5
2006-11-20Add in rom/rams for the nvram, hypervisor description, and partition ↵Gabe Black
description. --HG-- extra : convert_revision : a49de5fcfbea307c971964b8a68b95eb5d9a2bf4
2006-11-16Implement current working directory for LiveProcessesNathan Binkert
--HG-- extra : convert_revision : a2d3cf29ab65c61af27d82a8c421a41a19fd5aeb
2006-11-16Merge zower.eecs.umich.edu:/home/gblack/m5/newmemmemopsGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 74b2352b8f088e38cd1ecf3a8233b45df0476d93
2006-11-16Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
into zower.eecs.umich.edu:/home/gblack/m5/newmemmemops --HG-- extra : convert_revision : c49b760eac758dbde30867cb638fcb3b790f4721
2006-11-16Fixes for SPARC_FSGabe Black
configs/common/FSConfig.py: Make a SPARC system create an IO bus. src/python/m5/objects/T1000.py: Create a T1000 platform src/arch/sparc/miscregfile.cc: Initialize the strand status register to the value legion provides. src/cpu/exetrace.cc: Truncate an ExtMachInst to a MachInst before comparing with Legion. --HG-- extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
2006-11-14Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops --HG-- extra : convert_revision : 966246877ac1f1e6c2675d413b0b405cccfecbeb
2006-11-14Merge 141.212.106.238:/home/gblack/m5/newmemmemopsGabe Black
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem --HG-- extra : convert_revision : 8e805b9bbd5c64c2e5951384b3c6ef712062d08c
2006-11-14Create a stub t1000 platform.Gabe Black
--HG-- extra : convert_revision : 7e27b23b66c743b4625a1dd9d8d6ba61bff45168
2006-11-14Update phase param in the .py file for the cpusRon Dreslinski
--HG-- extra : convert_revision : cd2eb8c00adcb34b8693a4d1a66187927c0f6803
2006-11-13Expose debugBreakCycle through swig and get rid ofNathan Binkert
the Debug param context --HG-- extra : convert_revision : 40e9dcfa9faedbe0c90a43f908f20a7c14ded6a4
2006-11-11Fix TypoNathan Binkert
--HG-- extra : convert_revision : 4f5b610f364876b29ad0e04f1757e4b42d1f2bd8
2006-11-11Get rid of the ParamContext for pseudo instructions and moveNathan Binkert
the parameters to the BaseCPU object. --HG-- extra : convert_revision : 557292cffb40918133647b0c9ac653ee5112df2e
2006-11-09Get SPARC to the point that it starts running. Add ability to load the ROM ↵Ali Saidi
bin files, cleanup lockstep printing a bit Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work. SConstruct: Add TARGET_ISA to the list of environment variables that end up in the build_env for python configs/common/FSConfig.py: add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now src/SConscript: add a raw file object, at least until we get more info about how to compile openboot properly src/arch/sparc/system.cc: src/arch/sparc/system.hh: add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM src/base/loader/object_file.cc: src/base/loader/object_file.hh: add option to try raw when nothing works src/cpu/exetrace.cc: cleanup lockstep printing a little bit src/cpu/m5legion_interface.h: change the instruction to be 32 bits because it is src/mem/physical.cc: fix assert that doesn't work if memory starts somewhere above 0 src/python/m5/objects/BaseCPU.py: Add if statement to choose between sparc tlbs and alpha tlbs src/python/m5/objects/System.py: Add a sparc system that sets the rom addresses correctly src/python/m5/params.py: add the ability to add Addr() together --HG-- extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
2006-11-08Remove mem parameter. Should have been removed earlier.Kevin Lim
src/python/m5/objects/BaseCPU.py: These parameters should have been removed in an earlier push. --HG-- extra : convert_revision : 781b39ca370361e9568b1af0be96ff5848b1f3f4
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 23:31:32 +0000