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path: root/src/python/m5/objects
AgeCommit message (Expand)Author
2007-01-25Instead of passing an int to represent time between python and C++Nathan Binkert
2007-01-21add dumb time of day deviceAli Saidi
2007-01-09add memory mapped disk deviceAli Saidi
2007-01-03Add 'Time' as a parameter type that can accept variousNathan Binkert
2006-12-29Merge zizzer.eecs.umich.edu:/bk/newmemNathan Binkert
2006-12-29FormattingNathan Binkert
2006-12-27Bug fixes in the TLBAli Saidi
2006-12-15small change to eliminate address range overlap.Lisa Hsu
2006-12-12Merge zizzer:/bk/newmemLisa Hsu
2006-12-07get legion/m5 to first tlb miss faultAli Saidi
2006-12-04More changes to get SPARC fs closer. Now at 1.2M cycles before differenceAli Saidi
2006-12-02Fix help strings on GenRepl params.Steve Reinhardt
2006-11-30Load the hypervisor symbols twice, once with an address mask so that we can g...Ali Saidi
2006-11-22Added a parameter to set memory to zero. This is to support Legion, and once ...Gabe Black
2006-11-22Merge zizzer:/bk/sparcfsGabe Black
2006-11-20Add in rom/rams for the nvram, hypervisor description, and partition descript...Gabe Black
2006-11-16Implement current working directory for LiveProcessesNathan Binkert
2006-11-16Merge zower.eecs.umich.edu:/home/gblack/m5/newmemmemopsGabe Black
2006-11-16Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
2006-11-16Fixes for SPARC_FSGabe Black
2006-11-14Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
2006-11-14Merge 141.212.106.238:/home/gblack/m5/newmemmemopsGabe Black
2006-11-14Create a stub t1000 platform.Gabe Black
2006-11-14Update phase param in the .py file for the cpusRon Dreslinski
2006-11-13Expose debugBreakCycle through swig and get rid ofNathan Binkert
2006-11-11Fix TypoNathan Binkert
2006-11-11Get rid of the ParamContext for pseudo instructions and moveNathan Binkert
2006-11-09Get SPARC to the point that it starts running. Add ability to load the ROM bi...Ali Saidi
2006-11-08Remove mem parameter. Should have been removed earlier.Kevin Lim
2006-11-07Remove hack by setting configuration better.Kevin Lim
2006-11-06delete pcifake, tsunamifake. Combine BadAddr/IsaFake into oneAli Saidi
2006-11-02Have bus use the BadAddress device to handle bad addresses. The O3 CPU shoul...Kevin Lim
2006-10-24Merge zizzer:/bk/newmemAli Saidi
2006-10-20Use fixPacket function everywhere.Ron Dreslinski
2006-10-20still working on getting past initializationAli Saidi
2006-10-18Get rid of obsolete in-cache copy support.Steve Reinhardt
2006-10-17Enable MP systems via cmd-line flag in fs.py.Steve Reinhardt
2006-10-11More cache fixes. Atomic coherence now works as well.Ron Dreslinski
2006-10-09Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-10-09Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-10-09Make memtest work with 8 memtestersRon Dreslinski
2006-10-09Update the Memtester, commit a config file/test for it.Ron Dreslinski
2006-10-08Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-10-08bus changesGabe Black
2006-10-08Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)Steve Reinhardt
2006-10-08Clean up configs.Kevin Lim
2006-10-05Partial reimplementation of the bus. The "clock" and "width" parameters have ...Gabe Black
2006-10-02Updates to fix merge issues and bring almost everything up to working speed. ...Kevin Lim
2006-09-30Merge ktlim@zamp:./local/clean/o3-merge/m5Kevin Lim
2006-09-18add boiler plate intel nic codeAli Saidi
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