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path: root/src/python/m5/objects
AgeCommit message (Expand)Author
2010-09-12swig: make all generated files go into the m5.internal packageNathan Binkert
2010-09-09scons: Stop building the big monolithic swigged params moduleNathan Binkert
2010-09-09init: don't build files that centralize python and swig codeNathan Binkert
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
2007-05-19PhysicalMemory has vector of uniform ports instead of one special one.Steve Reinhardt
2007-05-10remove hit_latency and make latency do the right thingAli Saidi
2007-05-10add/update parameters for bus bridgeAli Saidi
2007-05-07fix partial writes with a functional memory hackAli Saidi
2007-03-29Override addPrivateSplitL1Caches function in order to automatically set the t...Kevin Lim
2007-03-26first bit of life from the intel gigabit modelAli Saidi
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
2007-03-03Add Iob and remove the fake deviceAli Saidi
2007-03-03Implement Niagara I/O interface and rework interruptsAli Saidi
2007-02-21Get rid of the ConsoleListener SimObject and just fold theNathan Binkert
2007-02-18Get rid of the Serialize and IntervalStats Param contextsNathan Binkert
2007-02-17Get rid of the Statistics and Statreset ParamContexts, andNathan Binkert
2007-02-13Make mulitple consoles work and be distinguishable from each otherAli Saidi
2007-02-13Merge all of the execution trace configuration stuff intoNathan Binkert
2007-02-09Get rid of the Trace ParamContext and give python directNathan Binkert
2007-01-31make sparc fs less chattyAli Saidi
2007-01-25Move time forward to Jan 1, 2009 and update statsNathan Binkert
2007-01-25Instead of passing an int to represent time between python and C++Nathan Binkert
2007-01-21add dumb time of day deviceAli Saidi
2007-01-09add memory mapped disk deviceAli Saidi
2007-01-03Add 'Time' as a parameter type that can accept variousNathan Binkert
2006-12-29Merge zizzer.eecs.umich.edu:/bk/newmemNathan Binkert
2006-12-29FormattingNathan Binkert
2006-12-27Bug fixes in the TLBAli Saidi
2006-12-15small change to eliminate address range overlap.Lisa Hsu
2006-12-12Merge zizzer:/bk/newmemLisa Hsu
2006-12-07get legion/m5 to first tlb miss faultAli Saidi
2006-12-04More changes to get SPARC fs closer. Now at 1.2M cycles before differenceAli Saidi
2006-12-02Fix help strings on GenRepl params.Steve Reinhardt
2006-11-30Load the hypervisor symbols twice, once with an address mask so that we can g...Ali Saidi
2006-11-22Added a parameter to set memory to zero. This is to support Legion, and once ...Gabe Black
2006-11-22Merge zizzer:/bk/sparcfsGabe Black
2006-11-20Add in rom/rams for the nvram, hypervisor description, and partition descript...Gabe Black
2006-11-16Implement current working directory for LiveProcessesNathan Binkert
2006-11-16Merge zower.eecs.umich.edu:/home/gblack/m5/newmemmemopsGabe Black
2006-11-16Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
2006-11-16Fixes for SPARC_FSGabe Black
2006-11-14Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
2006-11-14Merge 141.212.106.238:/home/gblack/m5/newmemmemopsGabe Black
2006-11-14Create a stub t1000 platform.Gabe Black
2006-11-14Update phase param in the .py file for the cpusRon Dreslinski
2006-11-13Expose debugBreakCycle through swig and get rid ofNathan Binkert
2006-11-11Fix TypoNathan Binkert
2006-11-11Get rid of the ParamContext for pseudo instructions and moveNathan Binkert
2006-11-09Get SPARC to the point that it starts running. Add ability to load the ROM bi...Ali Saidi
2006-11-08Remove mem parameter. Should have been removed earlier.Kevin Lim
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