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path: root/src/python/m5/params.py
AgeCommit message (Expand)Author
2017-11-13config: Add an Energy param type.Gabe Black
2017-11-13config: Export the "Current" param type from m5.params.Gabe Black
2017-11-13config: Simplify the definitions of the Voltage and Current params.Gabe Black
2017-09-26sim: Add a get_config_as_dict to the NullSimObject class.Gabe Black
2017-09-26sim: Give the NullSimObject singleton a _name.Gabe Black
2017-09-26sim: Add a NullSimObject.descendants function.Gabe Black
2017-09-26sim: Add a clear_parent function to NullSimObject.Gabe Black
2017-09-26sim: Check the SimObjectVector.has_parent function to use the "any" function.Gabe Black
2017-09-26sim: Only consider non-NULL elements in SimObjectVector.has_parent.Gabe Black
2017-09-26sim: Add a set_parent to NullSimObject which does nothing.Gabe Black
2017-05-31python: Fix unproxing of VectorParamsNikos Nikoleris
2017-05-02python: Remove SWIGAndreas Sandberg
2017-05-02python: Use PyBind11 instead of SWIG for Python wrappersAndreas Sandberg
2017-01-27python: Move native wrappers to the _m5 namespaceAndreas Sandberg
2016-09-13base: Output all AddrRange parameters to config.iniMatt Poremba
2016-05-27power: Allow voltage to be configured via cmd lineAkash Bagdia
2015-11-22config: Added missing types to JSON/INI Python readerAndrew Bardsley
2015-02-03base: Add XOR-based hashed address interleavingAndreas Hansson
2015-02-03config: Fix typo in Float paramGeoffrey Blake
2014-10-16config: Add the ability to read a config file using C++ and PythonAndreas Hansson
2014-10-09config: Add Current as a parameter typeAndreas Hansson
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-09-20config: Cleanup .json config file generationAndrew Bardsley
2014-09-09config: Fix vectorparam command line parsingGeoffrey Blake
2014-09-03config: Add port splicing capability to PortRef classGeoffrey Blake
2014-09-03config: Change parsing of Addr so hex values work from scriptsMitch Hayenga
2014-08-10config: Add hooks to enable new config sysGeoffrey Blake
2014-05-09cpu: Add flag name printing to StaticInstAndrew Bardsley
2014-05-09scons: Require SWIG >= 2.0.4 and remove vector typemapsCurtis Dunham
2014-01-24config: Make the Clock a Tick parameter like Latency/FrequencyAndreas Hansson
2013-10-31config: Fix handling of parents for simobject vectorsGeoffrey Blake
2013-10-17config: Fix ommission of number base in ethernet address paramGeoffrey Blake
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
2013-06-27config: Remove Clock parameter multiplicationAndreas Hansson
2013-02-19x86: Move APIC clock divider to PythonAndreas Hansson
2013-01-07mem: Add interleaving bits to the address rangesAndreas Hansson
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
2012-09-19AddrRange: Simplify AddrRange params Python hierarchyAndreas Hansson
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-05-23Config: Use the attribute naming and include ports in JSONAndreas Hansson
2012-05-23Config: Exit with fatal if a port is already connectedAndreas Hansson
2012-04-06python: added __nonzero__ function to SimObject Bool paramsBrad Beckmann
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2012-02-13MEM: Pass the ports from Python to C++ using the Swig paramsAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-01-17MEM: Removing the default port peer from Python portsAndreas Hansson
2012-01-09config: support outputing a pickle of the configuration treeAli Saidi
2012-01-09SWIG: Make gem5 compile and link with swig 2.0.4Andreas Hansson
2011-10-31GCC: Get everything working with gcc 4.6.1.Gabe Black