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path: root/src/python/m5/params.py
AgeCommit message (Expand)Author
2015-02-03base: Add XOR-based hashed address interleavingAndreas Hansson
2015-02-03config: Fix typo in Float paramGeoffrey Blake
2014-10-16config: Add the ability to read a config file using C++ and PythonAndreas Hansson
2014-10-09config: Add Current as a parameter typeAndreas Hansson
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-09-20config: Cleanup .json config file generationAndrew Bardsley
2014-09-09config: Fix vectorparam command line parsingGeoffrey Blake
2014-09-03config: Add port splicing capability to PortRef classGeoffrey Blake
2014-09-03config: Change parsing of Addr so hex values work from scriptsMitch Hayenga
2014-08-10config: Add hooks to enable new config sysGeoffrey Blake
2014-05-09cpu: Add flag name printing to StaticInstAndrew Bardsley
2014-05-09scons: Require SWIG >= 2.0.4 and remove vector typemapsCurtis Dunham
2014-01-24config: Make the Clock a Tick parameter like Latency/FrequencyAndreas Hansson
2013-10-31config: Fix handling of parents for simobject vectorsGeoffrey Blake
2013-10-17config: Fix ommission of number base in ethernet address paramGeoffrey Blake
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
2013-06-27config: Remove Clock parameter multiplicationAndreas Hansson
2013-02-19x86: Move APIC clock divider to PythonAndreas Hansson
2013-01-07mem: Add interleaving bits to the address rangesAndreas Hansson
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
2012-09-19AddrRange: Simplify AddrRange params Python hierarchyAndreas Hansson
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-05-23Config: Use the attribute naming and include ports in JSONAndreas Hansson
2012-05-23Config: Exit with fatal if a port is already connectedAndreas Hansson
2012-04-06python: added __nonzero__ function to SimObject Bool paramsBrad Beckmann
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2012-02-13MEM: Pass the ports from Python to C++ using the Swig paramsAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-01-17MEM: Removing the default port peer from Python portsAndreas Hansson
2012-01-09config: support outputing a pickle of the configuration treeAli Saidi
2012-01-09SWIG: Make gem5 compile and link with swig 2.0.4Andreas Hansson
2011-10-31GCC: Get everything working with gcc 4.6.1.Gabe Black
2011-10-20SimObject: add export_method* hooks to export C++ methods to PythonSteve Reinhardt
2011-10-20scons/swig: refactor some of the scons/SWIG codeSteve Reinhardt
2011-09-22params.py: enhance IpAddress param handlingSteve Reinhardt
2011-07-10O3: Make sure fetch doesn't go off into the weeds during speculation.Ali Saidi
2011-07-10Config: Add support for a Self.all proxy objectAli Saidi
2011-05-23config: reinstate implicit parenting on parameter assignmentSteve Reinhardt
2011-01-03Make commenting on close namespace brackets consistent.Steve Reinhardt
2010-12-20Params: Fix a broken error message in verifyIp.Gabe Black
2010-11-23Copyright: Add AMD copyright to the param changes I just made.Gabe Black
2010-11-23Params: Add parameter types for IP addresses in various forms.Gabe Black
2010-11-11Params: Fix an off by one error and a misleading comment.Gabe Black
2010-09-12swig: make all generated files go into the m5.internal packageNathan Binkert
2010-09-09scons: Stop building the big monolithic swigged params moduleNathan Binkert
2010-09-09scons: use code_formatter wherever we can in the build systemNathan Binkert
2010-08-17misc: add some AMD copyright noticesSteve Reinhardt
2010-08-17sim: clean up child handlingSteve Reinhardt
2010-08-17sim: fail on implicit creation of orphans via portsSteve Reinhardt