gem5 - gem5

Age	Commit message (Expand)	Author
2018-03-06	scons: Switch from the print statement to the print function.	Gabe Black
2017-11-13	config: Add an Energy param type.	Gabe Black
2017-11-13	config: Export the "Current" param type from m5.params.	Gabe Black
2017-11-13	config: Simplify the definitions of the Voltage and Current params.	Gabe Black
2017-09-26	sim: Add a get_config_as_dict to the NullSimObject class.	Gabe Black
2017-09-26	sim: Give the NullSimObject singleton a _name.	Gabe Black
2017-09-26	sim: Add a NullSimObject.descendants function.	Gabe Black
2017-09-26	sim: Add a clear_parent function to NullSimObject.	Gabe Black
2017-09-26	sim: Check the SimObjectVector.has_parent function to use the "any" function.	Gabe Black
2017-09-26	sim: Only consider non-NULL elements in SimObjectVector.has_parent.	Gabe Black
2017-09-26	sim: Add a set_parent to NullSimObject which does nothing.	Gabe Black
2017-05-31	python: Fix unproxing of VectorParams	Nikos Nikoleris
2017-05-02	python: Remove SWIG	Andreas Sandberg
2017-05-02	python: Use PyBind11 instead of SWIG for Python wrappers	Andreas Sandberg
2017-01-27	python: Move native wrappers to the _m5 namespace	Andreas Sandberg
2016-09-13	base: Output all AddrRange parameters to config.ini	Matt Poremba
2016-05-27	power: Allow voltage to be configured via cmd line	Akash Bagdia
2015-11-22	config: Added missing types to JSON/INI Python reader	Andrew Bardsley
2015-02-03	base: Add XOR-based hashed address interleaving	Andreas Hansson
2015-02-03	config: Fix typo in Float param	Geoffrey Blake
2014-10-16	config: Add the ability to read a config file using C++ and Python	Andreas Hansson
2014-10-09	config: Add Current as a parameter type	Andreas Hansson
2014-09-20	mem: Rename Bus to XBar to better reflect its behaviour	Andreas Hansson
2014-09-20	config: Cleanup .json config file generation	Andrew Bardsley
2014-09-09	config: Fix vectorparam command line parsing	Geoffrey Blake
2014-09-03	config: Add port splicing capability to PortRef class	Geoffrey Blake
2014-09-03	config: Change parsing of Addr so hex values work from scripts	Mitch Hayenga
2014-08-10	config: Add hooks to enable new config sys	Geoffrey Blake
2014-05-09	cpu: Add flag name printing to StaticInst	Andrew Bardsley
2014-05-09	scons: Require SWIG >= 2.0.4 and remove vector typemaps	Curtis Dunham
2014-01-24	config: Make the Clock a Tick parameter like Latency/Frequency	Andreas Hansson
2013-10-31	config: Fix handling of parents for simobject vectors	Geoffrey Blake
2013-10-17	config: Fix ommission of number base in ethernet address param	Geoffrey Blake
2013-08-19	power: Add voltage domains to the clock domains	Akash Bagdia
2013-06-27	config: Remove Clock parameter multiplication	Andreas Hansson
2013-02-19	x86: Move APIC clock divider to Python	Andreas Hansson
2013-01-07	mem: Add interleaving bits to the address ranges	Andreas Hansson
2012-09-19	AddrRange: Transition from Range<T> to AddrRange	Andreas Hansson
2012-09-19	AddrRange: Simplify AddrRange params Python hierarchy	Andreas Hansson
2012-09-07	Param: Transition to Cycles for relevant parameters	Andreas Hansson
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-05-23	Config: Use the attribute naming and include ports in JSON	Andreas Hansson
2012-05-23	Config: Exit with fatal if a port is already connected	Andreas Hansson
2012-04-06	python: added __nonzero__ function to SimObject Bool params	Brad Beckmann
2012-03-19	gcc: Clean-up of non-C++0x compliant code, first steps	Andreas Hansson
2012-02-13	MEM: Pass the ports from Python to C++ using the Swig params	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-01-17	MEM: Removing the default port peer from Python ports	Andreas Hansson
2012-01-09	config: support outputing a pickle of the configuration tree	Ali Saidi
2012-01-09	SWIG: Make gem5 compile and link with swig 2.0.4	Andreas Hansson