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path: root/src/python/m5/params.py
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2015-02-03base: Add XOR-based hashed address interleavingAndreas Hansson
This patch extends the current address interleaving with basic hashing support. Instead of directly comparing a number of address bits with a matching value, it is now possible to use two independent set of address bits XOR'ed together. This avoids issues where strided address patterns are heavily biased to a subset of the interleaved ranges.
2015-02-03config: Fix typo in Float paramGeoffrey Blake
The Float param was not settable on the command line due to a typo in the class definition in python/m5/params.py. This corrects the typo and allows floats to be set on the command line as intended.
2014-10-16config: Add the ability to read a config file using C++ and PythonAndreas Hansson
This patch adds the ability to load in config.ini files generated from gem5 into another instance of gem5 built without Python configuration support. The intended use case is for configuring gem5 when it is a library embedded in another simulation system. A parallel config file reader is also provided purely in Python to demonstrate the approach taken and to provided similar functionality for as-yet-unknown use models. The Python configuration file reader can read both .ini and .json files. C++ configuration file reading: A command line option has been added for scons to enable C++ configuration file reading: --with-cxx-config There is an example in util/cxx_config that shows C++ configuration in action. util/cxx_config/README explains how to build the example. Configuration is achieved by the object CxxConfigManager. It handles reading object descriptions from a CxxConfigFileBase object which wraps a config file reader. The wrapper class CxxIniFile is provided which wraps an IniFile for reading .ini files. Reading .json files from C++ would be possible with a similar wrapper and a JSON parser. After reading object descriptions, CxxConfigManager creates SimObjectParam-derived objects from the classes in the (generated with this patch) directory build/ARCH/cxx_config CxxConfigManager can then build SimObjects from those SimObjectParams (in an order dictated by the SimObject-value parameters on other objects) and bind ports of the produced SimObjects. A minimal set of instantiate-replacing member functions are provided by CxxConfigManager and few of the member functions of SimObject (such as drain) are extended onto CxxConfigManager. Python configuration file reading (configs/example/read_config.py): A Python version of the reader is also supplied with a similar interface to CxxConfigFileBase (In Python: ConfigFile) to config file readers. The Python config file reading will handle both .ini and .json files. The object construction strategy is slightly different in Python from the C++ reader as you need to avoid objects prematurely becoming the children of other objects when setting parameters. Port binding also needs to be strictly in the same port-index order as the original instantiation.
2014-10-09config: Add Current as a parameter typeAndreas Hansson
This patch adds the Python parameter type Current, which is used for the DRAM power modelling (to start with). With this addition we avoid implicit unit assumptions.
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus. As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet. --HG-- rename : src/mem/Bus.py => src/mem/XBar.py rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh rename : src/mem/bus.cc => src/mem/xbar.cc rename : src/mem/bus.hh => src/mem/xbar.hh
2014-09-20config: Cleanup .json config file generationAndrew Bardsley
This patch 'completes' .json config files generation by adding in the SimObject references and String-valued parameters not currently printed. TickParamValues are also changed to print in the same tick-value format as in .ini files. This allows .json files to describe a system as fully as the .ini files currently do. This patch adds a new function config_value (which mirrors ini_str) to each ParamValue and to SimObject. This function can then be explicitly changed to give different .json and .ini printing behaviour rather than being written in terms of ini_str.
2014-09-09config: Fix vectorparam command line parsingGeoffrey Blake
Parsing vectorparams from the command was slightly broken in that it wouldn't accept the input that the help message provided to the user and it didn't do the conversion on the second code path used to convert the string input to the actual internal representation. This patch fixes these bugs.
2014-09-03config: Add port splicing capability to PortRef classGeoffrey Blake
The new configuration scripts need the ability to splice a simobject between a pair of ports that are already connected. The primary use case is when a CommMonitor needs to be created after the system is configured and then spliced between the pair of ports it will monitor.
2014-09-03config: Change parsing of Addr so hex values work from scriptsMitch Hayenga
When passed from a configuration script with a hexadecimal value (like "0x80000000"), gem5 would error out. This is because it would call "toMemorySize" which requires the argument to end with a size specifier (like 1MB, etc). This modification makes it so raw hex values can be passed through Addr parameters from the configuration scripts.
2014-08-10config: Add hooks to enable new config sysGeoffrey Blake
This patch adds helper functions to SimObject.py, params.py and simulate.py to enable the new configuration system. Functions like enumerateParams() in SimObject lets the config system auto-generate command line options for simobjects to be modified on the command line. Params in params.py have __call__() added to their definition to allow the argparse module to use them as a type to check command input is in the proper format.
2014-05-09cpu: Add flag name printing to StaticInstAndrew Bardsley
This patch adds a the member function StaticInst::printFlags to allow all of an instruction's flags to be printed without using the individual is... member functions or resorting to exposing the 'flags' vector It also replaces the enum definition StaticInst::Flags with a Python-generated enumeration and adds to the enum generation mechanism in src/python/m5/params.py to allow Enums to be placed in namespaces other than Enums or, alternatively, in wrapper structs allowing them to be inherited by other classes (so populating that class's name-space with the enumeration element names).
2014-05-09scons: Require SWIG >= 2.0.4 and remove vector typemapsCurtis Dunham
SWIG commit fd666c1 (*) made it unnecessary for gem5 to have these typemaps to handle Vector types. * https://github.com/swig/swig/commit/fd666c1440628a847793bbe1333c27dfa2f757f0
2014-01-24config: Make the Clock a Tick parameter like Latency/FrequencyAndreas Hansson
This patch makes the Clock a TickParamValue just like Latency/Frequency. There is no longer any need to distinguish it (originally needed to support multiplication).
2013-10-31config: Fix handling of parents for simobject vectorsGeoffrey Blake
SimObjectVector objects did not provide the same interface to the _parent attribute through get_parent() like a normal SimObject. It also handled assigning a _parent incorrectly if objects in a SimObjectVector were changed post-creation, leading to errors later when the simulator tried to execute. This patch fixes these two omissions.
2013-10-17config: Fix ommission of number base in ethernet address paramGeoffrey Blake
The ethernet address param tries to convert a hexadecimal string using int() in python, which defaults to base 10, need to specify base 16 in this case.
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
This patch adds the notion of voltage domains, and groups clock domains that operate under the same voltage (i.e. power supply) into domains. Each clock domain is required to be associated with a voltage domain, and the latter requires the voltage to be explicitly set. A voltage domain is an independently controllable voltage supply being provided to section of the design. Thus, if you wish to perform dynamic voltage scaling on a CPU, its clock domain should be associated with a separate voltage domain. The current implementation of the voltage domain does not take into consideration cases where there are derived voltage domains running at ratio of native voltage domains, as with the case where there can be on-chip buck/boost (charge pumps) voltage regulation logic. The regression and configuration scripts are updated with a generic voltage domain for the system, and one for the CPUs.
2013-06-27config: Remove Clock parameter multiplicationAndreas Hansson
This patch removes the multiplication operator support for Clock parameters as this functionality is now achieved by creating derived clock domains. Nate, this one is for you.
2013-02-19x86: Move APIC clock divider to PythonAndreas Hansson
This patch moves the 16x APIC clock divider to the Python code to avoid the post-instantiation modifications to the clock. The x86 APIC was the only object setting the clock after creation time and this required some custom functionality and configuration. With this patch, the clock multiplier is moved to the Python code and the objects are instantiated with the appropriate clock.
2013-01-07mem: Add interleaving bits to the address rangesAndreas Hansson
This patch adds support for interleaving bits for the address ranges. What was previously just a start and end address, now has an additional three fields, for the high bit, and number of bits to use for interleaving, and a match value to compare against. If the number of interleaving bits is set to zero it is effectively disabled. A number of convenience functions are added to the range to enquire about the interleaving, its granularity and the number of stripes it is part of.
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
This patch takes the final plunge and transitions from the templated Range class to the more specific AddrRange. In doing so it changes the obvious Range<Addr> to AddrRange, and also bumps the range_map to be AddrRangeMap. In addition to the obvious changes, including the removal of redundant includes, this patch also does some house keeping in preparing for the introduction of address interleaving support in the ranges. The Range class is also stripped of all the functionality that is never used. --HG-- rename : src/base/range.hh => src/base/addr_range.hh rename : src/base/range_map.hh => src/base/addr_range_map.hh
2012-09-19AddrRange: Simplify AddrRange params Python hierarchyAndreas Hansson
This patch simplifies the Range object hierarchy in preparation for an address range class that also allows striping (e.g. selecting a few bits as matching in addition to the range). To extend the AddrRange class to an AddrRegion, the first step is to simplify the hierarchy such that we can make it as lean as possible before adding the new functionality. The only class using Range and MetaRange is AddrRange, and the three classes are now collapsed into one.
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
This patch is a first step to using Cycles as a parameter type. The main affected modules are the CPUs and the Ruby caches. There are definitely plenty more places that are affected, but this patch serves as a starting point to making the transition. An important part of this patch is to actually enable parameters to be specified as Param.Cycles which involves some changes to params.py.
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
This patch addresses the comments and feedback on the preceding patch that reworks the clocks and now more clearly shows where cycles (relative cycle counts) are used to express time. Instead of bumping the existing patch I chose to make this a separate patch, merely to try and focus the discussion around a smaller set of changes. The two patches will be pushed together though. This changes done as part of this patch are mostly following directly from the introduction of the wrapper class, and change enough code to make things compile and run again. There are definitely more places where int/uint/Tick is still used to represent cycles, and it will take some time to chase them all down. Similarly, a lot of parameters should be changed from Param.Tick and Param.Unsigned to Param.Cycles. In addition, the use of curTick is questionable as there should not be an absolute cycle. Potential solutions can be built on top of this patch. There is a similar situation in the o3 CPU where lastRunningCycle is currently counting in Cycles, and is still an absolute time. More discussion to be had in other words. An additional change that would be appropriate in the future is to perform a similar wrapping of Tick and probably also introduce a Ticks class along with suitable operators for all these classes.
2012-05-23Config: Use the attribute naming and include ports in JSONAndreas Hansson
This patch changes the organisation of the JSON output slightly to make it easier to traverse and use the files. Most importantly, the hierarchical dictionaries now use keys that correspond to the attribute names also in the case of VectorParams (used to be e.f. "cpu0 cpu1"). It also adds the name and the path to each SimObject directory entry. Before this patch, to get cpu0, you would have to query dict['system']['cpu0 cpu1'][0] and this could be a dict with 'cpu0' : { cpu parameters }. Now you use dict['system']['cpu'][0] and get { cpu parameters } (where one is "name" : "cpu0"). Additionally this patch includes more verbose information about the ports, specifying their role, and using a JSON array rather than a concatenated string for the peer.
2012-05-23Config: Exit with fatal if a port is already connectedAndreas Hansson
This patch turns the existing warning into a fatal, as there should never be any cases where a (non-vector) port is assigned to and then later connected to something else. If this behaviour is allowed, as it used to be, there are cases where the wrong number of C++ ports are created when instantiating objects with VectorPorts (obviously that could be fixed, but the better approach is to simply not allow it).
2012-04-06python: added __nonzero__ function to SimObject Bool paramsBrad Beckmann
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
This patch cleans up a number of minor issues aiming to get closer to compliance with the C++0x standard as interpreted by gcc and clang (compile with std=c++0x and -pedantic-errors). In particular, the patch cleans up enums where the last item was succeded by a comma, namespaces closed by a curcly brace followed by a semi-colon, and the use of the GNU-extension typeof (replaced by templated functions). It does not address variable-length arrays, zero-size arrays, anonymous structs, range expressions in switch statements, and the use of long long. The generated CPU code also has a large number of issues that remain to be fixed, mainly related to overflows in implicit constant conversion (due to shifts).
2012-02-13MEM: Pass the ports from Python to C++ using the Swig paramsAndreas Hansson
This patch adds basic information about the ports in the parameter classes to be passed from the Python world to the corresponding C++ object. Currently, the only information passed is the number of connected peers, which for a Port is either 0 or 1, and for a VectorPort reflects the size of the VectorPort. The default port of the bus had to be renamed to avoid using the name "default" as a field in the parameter class. It is possible to extend the Swig'ed information further and add e.g. a pair with a description and size.
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves.
2012-01-17MEM: Removing the default port peer from Python portsAndreas Hansson
In preparation for the introduction of Master and Slave ports, this patch removes the default port parameter in the Python port and thus forces the argument list of the Port to contain only the description. The drawback at this point is that the config port and dma port of PCI and DMA devices have to be connected explicitly. This is key for future diversification as the pio and config port are slaves, but the dma port is a master.
2012-01-09config: support outputing a pickle of the configuration treeAli Saidi
2012-01-09SWIG: Make gem5 compile and link with swig 2.0.4Andreas Hansson
To make gem5 compile and run with swig 2.0.4 a few minor fixes are necessary, the fail label issues by swig must not be treated as an error by gcc (tested with gcc 4.2.1), and the vector wrappers must have SWIGPY_SLICE_ARG defined which happens in pycontainer.swg, included through std_container.i. By adding the aforementioned include to the vector wrappers everything seems to work.
2011-10-31GCC: Get everything working with gcc 4.6.1.Gabe Black
And by "everything" I mean all the quick regressions.
2011-10-20SimObject: add export_method* hooks to export C++ methods to PythonSteve Reinhardt
Replace the (broken as of previous changeset) swig_objdecl() method that allowed/forced you to substitute a whole new C++ struct definition for SWIG to wrap with a set of export_method* hooks that let you just declare a set of C++ methods (or other declarations) that get inserted in the auto-generated struct. Restore the System get/setMemoryMode methods, and use this mechanism to specialize SimObject as well, eliminating teh need for sim_object.i. Needed bits of sim_object.i are moved to the new pyobject.i. Also sucked a little SimObject specialization into cxx_param_decl() allowing us to get rid of src/sim/sim_object_params.hh. Now the generation and wrapping of the base SimObject param struct is more in line with how derived objects are handled. --HG-- rename : src/python/swig/sim_object.i => src/python/swig/pyobject.i
2011-10-20scons/swig: refactor some of the scons/SWIG codeSteve Reinhardt
- Move the random bits of SWIG code generation out of src/SConscript file and into methods on the objects being wrapped. - Cleaned up some variable naming and added some comments to make the process a little clearer. - Did a little generated file/module renaming: - vptype_Foo now Foo_vector - init_Foo is now Foo_init This makes it easier to see all the Foo-related files in a sorted directory listing. - Made cxx_predecls and swig_predecls normal SimObject classmethods. - Got rid of swig_objdecls hook, even though this breaks the System objects get/setMemoryMode method exports. Will be fixing this in a future changeset.
2011-09-22params.py: enhance IpAddress param handlingSteve Reinhardt
Print IpAddress params in dot notation for readability. Properly compare IpAddress objects (by value and not object identity). Also fix up derived param classes (IpNetmask and IpWithPort) similarly.
2011-07-10O3: Make sure fetch doesn't go off into the weeds during speculation.Ali Saidi
2011-07-10Config: Add support for a Self.all proxy objectAli Saidi
2011-05-23config: reinstate implicit parenting on parameter assignmentSteve Reinhardt
Last summer's big rewrite of the initialization code (in particular cset 6efc3672733b) got rid of the implicit parenting that used to occur when an unparented SimObject was assigned as a parameter value to another SimObject. The idea was that the new adoptOrphanParams() step would catch these anyway so it was unnecessary. Unfortunately it turns out that adoptOrphanParams() has some inherent instability in that the parent that does the adoption depends on the config tree traversal order. Even making this order deterministic (e.g., by traversing children in alphabetical order) can introduce unwanted and unexpected hierarchy changes between similar configs (e.g., when adding a switch_cpu in place of a cpu), causing problems when trying to restore checkpoints across similar configs. The hierarchy created by implicit parenting is more stable and more controllable, so this patch turns that behavior back on. This patch also cleans up some long-standing holes regarding parenting of SimObjects that are created in class definitions (either in the body of the class, or as default parameters). To avoid breaking some existing config files, this necessitated changing the error on reparenting children to a warning. This change fixes another bug where attempting to print the prior error message would fail on reparenting SimObjectVectors because they lack a _parent attribute. Some further issues with SimObjectVectors were cleaned up by getting rid of the get_parent() call (which could cause errors with some SimObjectVectors where there was no single parent to return) with has_parent() (since all the uses of get_parent() were just boolean tests anyway). Finally, since the adoptOrphanParam() step turned out to be so problematic, we now issue a warning when it actually has to do an adoption. Future cleanup of config files will get rid of current warnings.
2011-01-03Make commenting on close namespace brackets consistent.Steve Reinhardt
Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript.
2010-12-20Params: Fix a broken error message in verifyIp.Gabe Black
2010-11-23Copyright: Add AMD copyright to the param changes I just made.Gabe Black
2010-11-23Params: Add parameter types for IP addresses in various forms.Gabe Black
New parameter forms are: IP address in the format "a.b.c.d" where a-d are from decimal 0 to 255. IP address with netmask which is an IP followed by "/n" where n is a netmask length in bits from decimal 0 to 32 or by "/e.f.g.h" where e-h are from decimal 0 to 255 and which is all 1 bits followed by all 0 bits when represented in binary. These can also be specified as an integral IP and netmask passed in separately. IP address with port which is an IP followed by ":p" where p is a port index from decimal 0 to 65535. These can also be specified as an integral IP and port value passed in separately.
2010-11-11Params: Fix an off by one error and a misleading comment.Gabe Black
2010-09-12swig: make all generated files go into the m5.internal packageNathan Binkert
This is necessary because versions of swig older than 1.3.39 fail to do the right thing and try to do relative imports for everything (even with the package= option to %module). Instead of putting params in the m5.internal.params package, put params in the m5.internal package and make all param modules start with param_. Same thing for m5.internal.enums. Also, stop importing all generated params into m5.objects. They are not necessary and now with everything using relative imports we wound up with pollution of the namespace (where builtin-range got overridden). --HG-- rename : src/python/m5/internal/enums/__init__.py => src/python/m5/internal/enums.py rename : src/python/m5/internal/params/__init__.py => src/python/m5/internal/params.py
2010-09-09scons: Stop building the big monolithic swigged params moduleNathan Binkert
kill params.i and create a separate .i for each object (param, enums, etc.)
2010-09-09scons: use code_formatter wherever we can in the build systemNathan Binkert
2010-08-17misc: add some AMD copyright noticesSteve Reinhardt
Meant to add these with the previous batch of csets.
2010-08-17sim: clean up child handlingSteve Reinhardt
The old code for handling SimObject children was kind of messy, with children stored both in _values and _children, and inconsistent and potentially buggy handling of SimObject vectors. Now children are always stored in _children, and SimObject vectors are consistently handled using the SimObjectVector class. Also, by deferring the parenting of SimObject-valued parameters until the end (instead of doing it at assignment), we eliminate the hole where one could assign a vector of SimObjects to a parameter then append to that vector, with the appended objects never getting parented properly. This patch induces small stats changes in tests with data races due to changes in the object creation & initialization order. The new code does object vectors in order and so should be more stable.
2010-08-17sim: fail on implicit creation of orphans via portsSteve Reinhardt
Orphan SimObjects (not in the config hierarchy) could get created implicitly if they have a port connection to a SimObject that is in the hierarchy. This means that there are objects on the C++ SimObject list (created via the C++ SimObject constructor call) that are unknown to Python and will get skipped if we walk the hierarchy from the Python side (as we are about to do). This patch detects this situation and prints an error message. Also fix the rubytester config script which happened to rely on this behavior.