gem5 - gem5

Age	Commit message (Expand)	Author
2015-02-03	base: Add XOR-based hashed address interleaving	Andreas Hansson
2015-02-03	config: Fix typo in Float param	Geoffrey Blake
2014-10-16	config: Add the ability to read a config file using C++ and Python	Andreas Hansson
2014-10-09	config: Add Current as a parameter type	Andreas Hansson
2014-09-20	mem: Rename Bus to XBar to better reflect its behaviour	Andreas Hansson
2014-09-20	config: Cleanup .json config file generation	Andrew Bardsley
2014-09-09	config: Fix vectorparam command line parsing	Geoffrey Blake
2014-09-03	config: Add port splicing capability to PortRef class	Geoffrey Blake
2014-09-03	config: Change parsing of Addr so hex values work from scripts	Mitch Hayenga
2014-08-10	config: Add hooks to enable new config sys	Geoffrey Blake
2014-05-09	cpu: Add flag name printing to StaticInst	Andrew Bardsley
2014-05-09	scons: Require SWIG >= 2.0.4 and remove vector typemaps	Curtis Dunham
2014-01-24	config: Make the Clock a Tick parameter like Latency/Frequency	Andreas Hansson
2013-10-31	config: Fix handling of parents for simobject vectors	Geoffrey Blake
2013-10-17	config: Fix ommission of number base in ethernet address param	Geoffrey Blake
2013-08-19	power: Add voltage domains to the clock domains	Akash Bagdia
2013-06-27	config: Remove Clock parameter multiplication	Andreas Hansson
2013-02-19	x86: Move APIC clock divider to Python	Andreas Hansson
2013-01-07	mem: Add interleaving bits to the address ranges	Andreas Hansson
2012-09-19	AddrRange: Transition from Range<T> to AddrRange	Andreas Hansson
2012-09-19	AddrRange: Simplify AddrRange params Python hierarchy	Andreas Hansson
2012-09-07	Param: Transition to Cycles for relevant parameters	Andreas Hansson
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-05-23	Config: Use the attribute naming and include ports in JSON	Andreas Hansson
2012-05-23	Config: Exit with fatal if a port is already connected	Andreas Hansson
2012-04-06	python: added __nonzero__ function to SimObject Bool params	Brad Beckmann
2012-03-19	gcc: Clean-up of non-C++0x compliant code, first steps	Andreas Hansson
2012-02-13	MEM: Pass the ports from Python to C++ using the Swig params	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-01-17	MEM: Removing the default port peer from Python ports	Andreas Hansson
2012-01-09	config: support outputing a pickle of the configuration tree	Ali Saidi
2012-01-09	SWIG: Make gem5 compile and link with swig 2.0.4	Andreas Hansson
2011-10-31	GCC: Get everything working with gcc 4.6.1.	Gabe Black
2011-10-20	SimObject: add export_method* hooks to export C++ methods to Python	Steve Reinhardt
2011-10-20	scons/swig: refactor some of the scons/SWIG code	Steve Reinhardt
2011-09-22	params.py: enhance IpAddress param handling	Steve Reinhardt
2011-07-10	O3: Make sure fetch doesn't go off into the weeds during speculation.	Ali Saidi
2011-07-10	Config: Add support for a Self.all proxy object	Ali Saidi
2011-05-23	config: reinstate implicit parenting on parameter assignment	Steve Reinhardt
2011-01-03	Make commenting on close namespace brackets consistent.	Steve Reinhardt
2010-12-20	Params: Fix a broken error message in verifyIp.	Gabe Black
2010-11-23	Copyright: Add AMD copyright to the param changes I just made.	Gabe Black
2010-11-23	Params: Add parameter types for IP addresses in various forms.	Gabe Black
2010-11-11	Params: Fix an off by one error and a misleading comment.	Gabe Black
2010-09-12	swig: make all generated files go into the m5.internal package	Nathan Binkert
2010-09-09	scons: Stop building the big monolithic swigged params module	Nathan Binkert
2010-09-09	scons: use code_formatter wherever we can in the build system	Nathan Binkert
2010-08-17	misc: add some AMD copyright notices	Steve Reinhardt
2010-08-17	sim: clean up child handling	Steve Reinhardt
2010-08-17	sim: fail on implicit creation of orphans via ports	Steve Reinhardt