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directly configured by python. Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.
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extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
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so things are organized in a more sensible manner. Take apart
finalInit and expose the individual functions which are now
called from python. Make checkpointing a bit easier to use.
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extra : convert_revision : f470ddabbb47103e7b4734ef753c40089f2dcd9d
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pass the tuple of python's struct_time and interpret that.
Fixes a problem where the local timezone leaked into the time
calculation. Also fix things so that the unix, python, and RTC
data sheets all get the right time. Provide both years since 1900
and BCD two digit year.
Put the date back at 1/1/2006 for now.
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extra : convert_revision : 473244572f468de2cb579a3dd7ae296a6f81f5d7
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formats for time (strings, datetime objects, etc.)
Advance system time to 1/1/2009
Clean up time management code a little bit
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extra : convert_revision : 28ebecc7ea6b12f4345c77a9a6b4bdf2e752c4f8
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extra : convert_revision : 2ccb75b0912a384789458710fd9bbb65626f839e
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Rename cc_main to internal.main
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extra : convert_revision : e938005f600fbf8a43435e29426a948f4501f072
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bin files, cleanup lockstep printing a bit
Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work.
SConstruct:
Add TARGET_ISA to the list of environment variables that end up in the build_env for python
configs/common/FSConfig.py:
add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now
src/SConscript:
add a raw file object, at least until we get more info about how to compile openboot properly
src/arch/sparc/system.cc:
src/arch/sparc/system.hh:
add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM
src/base/loader/object_file.cc:
src/base/loader/object_file.hh:
add option to try raw when nothing works
src/cpu/exetrace.cc:
cleanup lockstep printing a little bit
src/cpu/m5legion_interface.h:
change the instruction to be 32 bits because it is
src/mem/physical.cc:
fix assert that doesn't work if memory starts somewhere above 0
src/python/m5/objects/BaseCPU.py:
Add if statement to choose between sparc tlbs and alpha tlbs
src/python/m5/objects/System.py:
Add a sparc system that sets the rom addresses correctly
src/python/m5/params.py:
add the ability to add Addr() together
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extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
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extra : convert_revision : 76b16fe2926611bd1c12c8ad7392355ad30a5138
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Includes support for printing readable VectorPort and Proxy names
(via __str__).
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extra : convert_revision : c48534a498b3036fe6ac45ff1606656546c79afb
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Significant revamp of Port code.
Some cleanup of SimObject code too, particularly to
make the SimObject and MetaSimObject implementations of
__setattr__ more consistent.
Unproxy code split out of print_ini().
src/python/m5/multidict.py:
Make get() return None by default, to match semantics
of built-in dictionary objects.
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extra : convert_revision : db73b6cdd004a82a08b2402afd1e16544cb902a4
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extra : convert_revision : 703d3a57250613315735709de8f40a9956cee6e2
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and resulting recursive import trickiness.
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extra : convert_revision : 1ea93861eb8d260c9f3920dda0b8106db3e03705
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Some tweaking to deal with mutually recursive imports.
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rename : src/python/m5/config.py => src/python/m5/SimObject.py
extra : convert_revision : 166f7bfabfd20100e93d26a89382469465859988
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