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path: root/src/python/m5/simulate.py
AgeCommit message (Expand)Author
2018-03-06scons: Switch from the print statement to the print function.Gabe Black
2017-05-09misc: Expose the listener loopbackOnly function to python.Gabe Black
2017-05-02python: Remove SWIGAndreas Sandberg
2017-01-27python: Move native wrappers to the _m5 namespaceAndreas Sandberg
2016-04-06misc: Bail out of DVFS dot if we cannot resolve the domainsSascha Bischoff
2015-12-15misc: Add secondary dot output for DVFS domainsSascha Bischoff
2015-11-26sim: Add support for forkingAndreas Sandberg
2015-11-26sim: Add support for notifying Drainable objects of a forkAndreas Sandberg
2015-07-07sim: Decouple draining from the SimObject hierarchyAndreas Sandberg
2015-07-07python: Remove redundant drain when changing memory modesAndreas Sandberg
2014-10-11sim: draining bug for fast-forwaring multiple coresAndrew Lukefahr
2014-01-24base: add support for probe points and common probesMatt Horsnell
2013-12-03sim: reset stats after startupNilay Vaish
2013-11-25sim: simulate with multiple threads and event queuesSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2013-11-14tests: suppress output on switcheroo testsSteve Reinhardt
2013-07-18sim: Make MaxTick in Python match the one in C++Andreas Hansson
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-02-15config: Move CPU handover logic to m5.switchCpus()Andreas Sandberg
2013-01-07cpu: Introduce sanity checks when switching between CPUsAndreas Sandberg
2012-11-02sim: Add drain methods to request additional cleanup operationsAndreas Sandberg
2012-11-02python: Rename doDrain()->drain() and make it do the right thingAndreas Sandberg
2012-11-02sim: Reuse the code to change memory mode.Andreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02Partly revert [4f54b0f229b5] and move draining to m5.changeToTimingAndreas Sandberg
2012-09-25Statistics: Add a function to configure periodic stats dumpingSascha Bischoff
2012-09-25sim: Move CPU-specific methods from SimObject to the BaseCPU classAndreas Sandberg
2012-09-25sim: Remove SimObject::setMemoryModeAndreas Sandberg
2012-09-12Standard Switch: Drain the system before switching CPUsJoel Hestness
2012-09-07sim: Remove the unused SimObject::regFormulas methodAndreas Sandberg
2012-05-10DOT: improved dot-based system visualizationUri Wiener
2012-05-10DOT: fixed broken code for visualizing configuration using dotUri Wiener
2012-01-10config: Fix json output for Python lt 2.6.Ali Saidi
2012-01-09config: support outputing a pickle of the configuration treeAli Saidi
2011-05-12stats: move code that loops over all stats into pythonNathan Binkert
2011-04-20fix some build problems from prior changesetsNathan Binkert
2011-04-15python: cleanup python code so stuff doesn't automatically happen at startupNathan Binkert
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2010-08-17misc: add some AMD copyright noticesSteve Reinhardt
2010-08-17sim: revamp unserialization procedureSteve Reinhardt
2010-08-17sim: fold checkpoint restore code into instantiate()Steve Reinhardt
2010-08-17sim: clean up child handlingSteve Reinhardt
2010-08-17sim: move iterating over SimObjects into Python.Steve Reinhardt
2010-08-17sim: make Python Root object a singletonSteve Reinhardt
2010-07-05sim: fold StartupCallback into SimObjectSteve Reinhardt
2010-02-23stats: this makes some fixes to AverageStat and AverageVector.Lisa Hsu
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
2009-03-05stats: create an enable phase, and a prepare phase.Nathan Binkert
2008-12-08output: Change default output directory and files and update tests.Nathan Binkert
2008-08-03sockets: Add a function to disable all listening sockets.Nathan Binkert
2007-08-30python: Write configuration file without reassigning sys.stdout.Miles Kaufmann