gem5 - gem5

Age	Commit message (Collapse)	Author
2017-09-26	util: Make dot_writer ignore NULL simobjects.	Gabe Black
	Also centralize the code which iterates over the parameters of a simnode's children, and remove a copy/paste block of code in the DVFS block of code. Change-Id: I01305fbff59346010780ee386ba97ad9106b1f5d Reviewed-on: https://gem5-review.googlesource.com/4849 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2016-04-06	misc: Bail out of DVFS dot if we cannot resolve the domains	Sascha Bischoff
	This changeset updates the dot output to bail out if it is unable to resolve the voltage or clock domains (which will cause it to raise an AttributeError). Additionally, the DVFS dot output is disabled by default for speed purposes. Minor fixup for 0aeca8f.
2015-12-15	misc: Add secondary dot output for DVFS domains	Sascha Bischoff
	This patch adds a secondary dot output file which shows the DVFS domains. This has been done separately for now to avoid cluttering the already existing diagram. Due to the way that the clock domains are assigned to components in gem5, this output must be generated after the C++ objects have been instantiated. This further motivates the need to generate this file separately to the current dot output, and not to replace it entirely.
2014-09-20	mem: Rename Bus to XBar to better reflect its behaviour	Andreas Hansson
	This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus. As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet. --HG-- rename : src/mem/Bus.py => src/mem/XBar.py rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh rename : src/mem/bus.cc => src/mem/xbar.cc rename : src/mem/bus.hh => src/mem/xbar.hh
2014-04-23	misc: Proper type check and import for PortRef	Sascha Bischoff
	Rewriting the type checking around PortRef, which was interacting strangely with other Python scripts. Tested-by: stephan.diestelhorst@arm.com
2013-09-04	util: Add ini string as tooltip info in dot output	Andreas Hansson
	This patch adds the config ini string as a tooltip that can be displayed in most browsers rendering the resulting svg. Certain characters are modified for HTML output. Tested on chrome and firefox.
2013-09-04	util: Add colours to the dot output	Andreas Hansson
	This patch is adding a splash of colour to the dot output to make it easier to distinguish objects of different types. As a bonus, the pastel-colour palette also makes the output look like a something from the 21st century.
2013-09-04	util: Add class name to dot graph and output to svg	Andreas Hansson
	This patch adds the class name to the label, creates some more space by increasing the rank separation, and additionally outputs the graph as an editable SVG in addition to the PDF.
2013-02-15	base: Add warn() and inform() to m5.utils for use from python	Sascha Bischoff
	This patch adds two fuctions to m5.util, warn and inform, which mirror those found in the C++ side of gem5. These are added in addition to the already existing m5.util.panic and m5.util.fatal which already mirror the C++ functionality. This ensures that warning and information messages generated by python are in the same format as those generated by C++. Occurrences of print "Warning: %s..." % name have been replaced with warn("%s...", name)
2012-05-10	DOT: improved dot-based system visualization	Uri Wiener
	Revised system visualization to reflect structure and memory hierarchy. Improved visualization: less congested and cluttered; more colorful. Nodes reflect components; directed edges reflect dirctional relation, from a master port to a slave port. Requires pydot.