summaryrefslogtreecommitdiff
path: root/src/python/m5
AgeCommit message (Expand)Author
2015-07-07sim: Decouple draining from the SimObject hierarchyAndreas Sandberg
2015-07-07sim: Move mem(Writeback|Invalidate) to SimObjectAndreas Sandberg
2015-07-07python: Remove redundant drain when changing memory modesAndreas Sandberg
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-03-23misc: quote args in echoed command lineSteve Reinhardt
2015-02-03base: Add XOR-based hashed address interleavingAndreas Hansson
2015-02-03config: Fix typo in Float paramGeoffrey Blake
2014-12-02scons: Ensure dictionary iteration is sorted by keyAndreas Hansson
2014-11-12sim: Sort SimObject descendants and portsAndreas Hansson
2014-10-16config: Add the ability to read a config file using C++ and PythonAndreas Hansson
2014-10-16config: Add a --without-python option to build processAndrew Bardsley
2014-10-11sim: draining bug for fast-forwaring multiple coresAndrew Lukefahr
2014-10-09config: Add Current as a parameter typeAndreas Hansson
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-09-20config: Cleanup .json config file generationAndrew Bardsley
2014-09-09config: Fix vectorparam command line parsingGeoffrey Blake
2014-09-03config: Add port splicing capability to PortRef classGeoffrey Blake
2014-09-03config: Change parsing of Addr so hex values work from scriptsMitch Hayenga
2014-08-10config: Add hooks to enable new config sysGeoffrey Blake
2014-05-09cpu: Add flag name printing to StaticInstAndrew Bardsley
2014-05-09config: Avoid generating a reference to myself for Parent.anyGeoffrey Blake
2014-05-09scons: Require SWIG >= 2.0.4 and remove vector typemapsCurtis Dunham
2014-04-23misc: Proper type check and import for PortRefSascha Bischoff
2014-02-10stats: better error message for uninitialized statisticCurtis Dunham
2014-03-23misc: Fix -q (quiet) flagStan Czerniawski
2014-01-24base: add support for probe points and common probesMatt Horsnell
2014-01-24config: Make the Clock a Tick parameter like Latency/FrequencyAndreas Hansson
2014-01-03python: provide better error message for wrapped C++ methodsSteve Reinhardt
2014-01-03python: don't die on assignment to cloned objectSteve Reinhardt
2013-12-03sim: reset stats after startupNilay Vaish
2013-11-25sim: simulate with multiple threads and event queuesSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2013-11-14tests: suppress output on switcheroo testsSteve Reinhardt
2013-11-01sim: Clarify the difference between tracing and debuggingAndreas Hansson
2013-10-31config: Fix handling of parents for simobject vectorsGeoffrey Blake
2013-10-17config: Fix ommission of number base in ethernet address paramGeoffrey Blake
2013-10-17config: Fix for port references generated multiple timesGeoffrey Blake
2013-09-18swig: Fix issue with circular import in 2.0.9/2.0.10Andreas Hansson
2013-09-04util: Add ini string as tooltip info in dot outputAndreas Hansson
2013-09-04util: Add colours to the dot outputAndreas Hansson
2013-09-04util: Add class name to dot graph and output to svgAndreas Hansson
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
2013-07-18sim: Make MaxTick in Python match the one in C++Andreas Hansson
2013-06-27config: Remove Clock parameter multiplicationAndreas Hansson
2013-02-19x86: Move APIC clock divider to PythonAndreas Hansson
2013-02-15base: Add warn() and inform() to m5.utils for use from pythonSascha Bischoff
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-02-15config: Move CPU handover logic to m5.switchCpus()Andreas Sandberg
2013-02-10base: Add support for newer versions of IPythonAndreas Sandberg
2013-02-10base: Fix broken IPython argument handlingAndreas Sandberg
2013-01-07cpu: Introduce sanity checks when switching between CPUsAndreas Sandberg
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 07:30:01 +0000