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Author
2013-07-18
sim: Make MaxTick in Python match the one in C++
Andreas Hansson
2013-06-27
config: Remove Clock parameter multiplication
Andreas Hansson
2013-02-19
x86: Move APIC clock divider to Python
Andreas Hansson
2013-02-15
base: Add warn() and inform() to m5.utils for use from python
Sascha Bischoff
2013-02-15
sim: Add a system-global option to bypass caches
Andreas Sandberg
2013-02-15
config: Move CPU handover logic to m5.switchCpus()
Andreas Sandberg
2013-02-10
base: Add support for newer versions of IPython
Andreas Sandberg
2013-02-10
base: Fix broken IPython argument handling
Andreas Sandberg
2013-01-07
cpu: Introduce sanity checks when switching between CPUs
Andreas Sandberg
2013-01-07
mem: Add interleaving bits to the address ranges
Andreas Hansson
2013-01-07
config: Traverse lists when visiting children in all proxy
Andreas Hansson
2012-11-02
sim: Add drain methods to request additional cleanup operations
Andreas Sandberg
2012-11-02
sim: Add SWIG interface for Serializable
Andreas Sandberg
2012-11-02
python: Rename doDrain()->drain() and make it do the right thing
Andreas Sandberg
2012-11-02
sim: Reuse the code to change memory mode.
Andreas Sandberg
2012-11-02
sim: Move the draining interface into a separate base class
Andreas Sandberg
2012-11-02
sim: Include object header files in SWIG interfaces
Andreas Sandberg
2012-11-02
Partly revert [4f54b0f229b5] and move draining to m5.changeToTiming
Andreas Sandberg
2012-10-15
Param: Fix proxy traversal to support chained proxies
Andreas Hansson
2012-09-25
Statistics: Add a function to configure periodic stats dumping
Sascha Bischoff
2012-09-25
sim: Move CPU-specific methods from SimObject to the BaseCPU class
Andreas Sandberg
2012-09-25
sim: Remove SimObject::setMemoryMode
Andreas Sandberg
2012-09-19
AddrRange: Transition from Range<T> to AddrRange
Andreas Hansson
2012-09-19
AddrRange: Simplify AddrRange params Python hierarchy
Andreas Hansson
2012-09-12
Standard Switch: Drain the system before switching CPUs
Joel Hestness
2012-09-07
sim: Remove the unused SimObject::regFormulas method
Andreas Sandberg
2012-09-07
Param: Transition to Cycles for relevant parameters
Andreas Hansson
2012-08-28
Clock: Add a Cycles wrapper class and use where applicable
Andreas Hansson
2012-07-10
ruby: changes how Topologies are created
Brad Beckmann
2012-06-05
stats: Provide a mechanism to get a callback when stats are dumped.
Mitchell Hayenga
2012-05-23
Config: Use the attribute naming and include ports in JSON
Andreas Hansson
2012-05-23
Config: Exit with fatal if a port is already connected
Andreas Hansson
2012-05-10
DOT: improved dot-based system visualization
Uri Wiener
2012-05-10
DOT: fixed broken code for visualizing configuration using dot
Uri Wiener
2012-05-10
stats: track if the stats have been enabled and prevent requesting master id
Ali Saidi
2012-04-14
Regression: Add ANSI colours to highlight test status
Andreas Hansson
2012-04-06
python: added __nonzero__ function to SimObject Bool params
Brad Beckmann
2012-04-05
Python: Make the All proxy traverse SimObject children as well
Andreas Hansson
2012-03-21
Python: Fix a conditional expression that requires Python 2.5
Andreas Hansson
2012-03-19
gcc: Clean-up of non-C++0x compliant code, first steps
Andreas Hansson
2012-03-19
scripts: Fix to ensure that port connection count is always set
Andreas Hansson
2012-02-29
SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1
Andreas Hansson
2012-02-20
SimObject: make get_config_as_dict() tolerate undefined params
Steve Reinhardt
2012-02-13
MEM: Pass the ports from Python to C++ using the Swig params
Andreas Hansson
2012-02-13
MEM: Introduce the master/slave port roles in the Python classes
Andreas Hansson
2012-01-31
clang: Enable compiling gem5 using clang 2.9 and 3.0
Koan-Sin Tan
2012-01-17
MEM: Removing the default port peer from Python ports
Andreas Hansson
2012-01-10
Automated merge with ssh://repo.gem5.org/gem5
Ali Saidi
2012-01-10
config: Fix json output for Python lt 2.6.
Ali Saidi
2012-01-09
Config: Fix issue with JSON output
Ali Saidi
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