summaryrefslogtreecommitdiff
path: root/src/python/m5
AgeCommit message (Expand)Author
2007-02-17Default to tracing being disabled in C++, it will be turnedNathan Binkert
2007-02-13Make mulitple consoles work and be distinguishable from each otherAli Saidi
2007-02-13Merge all of the execution trace configuration stuff intoNathan Binkert
2007-02-13Rearrange traceflags.py so that the file generation only happens ifNathan Binkert
2007-02-10Clean up tracing stuff more, get rid of the trace log sinceNathan Binkert
2007-02-09Clean up from my last commit to the trace stuff.Nathan Binkert
2007-02-09Get rid of the Trace ParamContext and give python directNathan Binkert
2007-01-31make sparc fs less chattyAli Saidi
2007-01-25Move time forward to Jan 1, 2009 and update statsNathan Binkert
2007-01-25Instead of passing an int to represent time between python and C++Nathan Binkert
2007-01-21add dumb time of day deviceAli Saidi
2007-01-09add memory mapped disk deviceAli Saidi
2007-01-03set __name__ in the root m5 script to __m5_main__ so we canNathan Binkert
2007-01-03Add 'Time' as a parameter type that can accept variousNathan Binkert
2006-12-29Merge zizzer.eecs.umich.edu:/bk/newmemNathan Binkert
2006-12-29FormattingNathan Binkert
2006-12-27Bug fixes in the TLBAli Saidi
2006-12-15small change to eliminate address range overlap.Lisa Hsu
2006-12-12Merge zizzer:/bk/newmemLisa Hsu
2006-12-07get legion/m5 to first tlb miss faultAli Saidi
2006-12-04More changes to get SPARC fs closer. Now at 1.2M cycles before differenceAli Saidi
2006-12-02Support better param conversions to/from numeric subclasses.Steve Reinhardt
2006-12-02Fix help strings on GenRepl params.Steve Reinhardt
2006-11-30Load the hypervisor symbols twice, once with an address mask so that we can g...Ali Saidi
2006-11-22Added a parameter to set memory to zero. This is to support Legion, and once ...Gabe Black
2006-11-22Merge zizzer:/bk/sparcfsGabe Black
2006-11-20Add in rom/rams for the nvram, hypervisor description, and partition descript...Gabe Black
2006-11-16Implement current working directory for LiveProcessesNathan Binkert
2006-11-16Merge zower.eecs.umich.edu:/home/gblack/m5/newmemmemopsGabe Black
2006-11-16Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
2006-11-16Fixes for SPARC_FSGabe Black
2006-11-14Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
2006-11-14Merge 141.212.106.238:/home/gblack/m5/newmemmemopsGabe Black
2006-11-14Create a stub t1000 platform.Gabe Black
2006-11-14Update phase param in the .py file for the cpusRon Dreslinski
2006-11-13Expose debugBreakCycle through swig and get rid ofNathan Binkert
2006-11-12Create a module called internal where swigged stuff goes.Nathan Binkert
2006-11-11Fix TypoNathan Binkert
2006-11-11Get rid of the ParamContext for pseudo instructions and moveNathan Binkert
2006-11-09Get SPARC to the point that it starts running. Add ability to load the ROM bi...Ali Saidi
2006-11-08simplify maxtick parsing in both the python and the c++.Lisa Hsu
2006-11-08Remove mem parameter. Should have been removed earlier.Kevin Lim
2006-11-08Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-11-07add code to operate in lockstep with legionAli Saidi
2006-11-07Fix error message.Kevin Lim
2006-11-07Remove hack by setting configuration better.Kevin Lim
2006-11-06delete pcifake, tsunamifake. Combine BadAddr/IsaFake into oneAli Saidi
2006-11-02Have bus use the BadAddress device to handle bad addresses. The O3 CPU shoul...Kevin Lim
2006-10-24Merge zizzer:/bk/newmemAli Saidi
2006-10-23Merge zizzer:/bk/newmemLisa Hsu
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 23:19:43 +0000