gem5 - gem5

Age	Commit message (Expand)	Author
2014-09-03	config: Add port splicing capability to PortRef class	Geoffrey Blake
2014-09-03	config: Change parsing of Addr so hex values work from scripts	Mitch Hayenga
2014-08-10	config: Add hooks to enable new config sys	Geoffrey Blake
2014-05-09	cpu: Add flag name printing to StaticInst	Andrew Bardsley
2014-05-09	config: Avoid generating a reference to myself for Parent.any	Geoffrey Blake
2014-05-09	scons: Require SWIG >= 2.0.4 and remove vector typemaps	Curtis Dunham
2014-04-23	misc: Proper type check and import for PortRef	Sascha Bischoff
2014-02-10	stats: better error message for uninitialized statistic	Curtis Dunham
2014-03-23	misc: Fix -q (quiet) flag	Stan Czerniawski
2014-01-24	base: add support for probe points and common probes	Matt Horsnell
2014-01-24	config: Make the Clock a Tick parameter like Latency/Frequency	Andreas Hansson
2014-01-03	python: provide better error message for wrapped C++ methods	Steve Reinhardt
2014-01-03	python: don't die on assignment to cloned object	Steve Reinhardt
2013-12-03	sim: reset stats after startup	Nilay Vaish
2013-11-25	sim: simulate with multiple threads and event queues	Steve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2013-11-14	tests: suppress output on switcheroo tests	Steve Reinhardt
2013-11-01	sim: Clarify the difference between tracing and debugging	Andreas Hansson
2013-10-31	config: Fix handling of parents for simobject vectors	Geoffrey Blake
2013-10-17	config: Fix ommission of number base in ethernet address param	Geoffrey Blake
2013-10-17	config: Fix for port references generated multiple times	Geoffrey Blake
2013-09-18	swig: Fix issue with circular import in 2.0.9/2.0.10	Andreas Hansson
2013-09-04	util: Add ini string as tooltip info in dot output	Andreas Hansson
2013-09-04	util: Add colours to the dot output	Andreas Hansson
2013-09-04	util: Add class name to dot graph and output to svg	Andreas Hansson
2013-08-19	power: Add voltage domains to the clock domains	Akash Bagdia
2013-07-18	sim: Make MaxTick in Python match the one in C++	Andreas Hansson
2013-06-27	config: Remove Clock parameter multiplication	Andreas Hansson
2013-02-19	x86: Move APIC clock divider to Python	Andreas Hansson
2013-02-15	base: Add warn() and inform() to m5.utils for use from python	Sascha Bischoff
2013-02-15	sim: Add a system-global option to bypass caches	Andreas Sandberg
2013-02-15	config: Move CPU handover logic to m5.switchCpus()	Andreas Sandberg
2013-02-10	base: Add support for newer versions of IPython	Andreas Sandberg
2013-02-10	base: Fix broken IPython argument handling	Andreas Sandberg
2013-01-07	cpu: Introduce sanity checks when switching between CPUs	Andreas Sandberg
2013-01-07	mem: Add interleaving bits to the address ranges	Andreas Hansson
2013-01-07	config: Traverse lists when visiting children in all proxy	Andreas Hansson
2012-11-02	sim: Add drain methods to request additional cleanup operations	Andreas Sandberg
2012-11-02	sim: Add SWIG interface for Serializable	Andreas Sandberg
2012-11-02	python: Rename doDrain()->drain() and make it do the right thing	Andreas Sandberg
2012-11-02	sim: Reuse the code to change memory mode.	Andreas Sandberg
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-11-02	Partly revert [4f54b0f229b5] and move draining to m5.changeToTiming	Andreas Sandberg
2012-10-15	Param: Fix proxy traversal to support chained proxies	Andreas Hansson
2012-09-25	Statistics: Add a function to configure periodic stats dumping	Sascha Bischoff
2012-09-25	sim: Move CPU-specific methods from SimObject to the BaseCPU class	Andreas Sandberg
2012-09-25	sim: Remove SimObject::setMemoryMode	Andreas Sandberg
2012-09-19	AddrRange: Transition from Range<T> to AddrRange	Andreas Hansson
2012-09-19	AddrRange: Simplify AddrRange params Python hierarchy	Andreas Hansson
2012-09-12	Standard Switch: Drain the system before switching CPUs	Joel Hestness