index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
python
/
m5
Age
Commit message (
Expand
)
Author
2013-12-03
sim: reset stats after startup
Nilay Vaish
2013-11-25
sim: simulate with multiple threads and event queues
Steve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2013-11-14
tests: suppress output on switcheroo tests
Steve Reinhardt
2013-11-01
sim: Clarify the difference between tracing and debugging
Andreas Hansson
2013-10-31
config: Fix handling of parents for simobject vectors
Geoffrey Blake
2013-10-17
config: Fix ommission of number base in ethernet address param
Geoffrey Blake
2013-10-17
config: Fix for port references generated multiple times
Geoffrey Blake
2013-09-18
swig: Fix issue with circular import in 2.0.9/2.0.10
Andreas Hansson
2013-09-04
util: Add ini string as tooltip info in dot output
Andreas Hansson
2013-09-04
util: Add colours to the dot output
Andreas Hansson
2013-09-04
util: Add class name to dot graph and output to svg
Andreas Hansson
2013-08-19
power: Add voltage domains to the clock domains
Akash Bagdia
2013-07-18
sim: Make MaxTick in Python match the one in C++
Andreas Hansson
2013-06-27
config: Remove Clock parameter multiplication
Andreas Hansson
2013-02-19
x86: Move APIC clock divider to Python
Andreas Hansson
2013-02-15
base: Add warn() and inform() to m5.utils for use from python
Sascha Bischoff
2013-02-15
sim: Add a system-global option to bypass caches
Andreas Sandberg
2013-02-15
config: Move CPU handover logic to m5.switchCpus()
Andreas Sandberg
2013-02-10
base: Add support for newer versions of IPython
Andreas Sandberg
2013-02-10
base: Fix broken IPython argument handling
Andreas Sandberg
2013-01-07
cpu: Introduce sanity checks when switching between CPUs
Andreas Sandberg
2013-01-07
mem: Add interleaving bits to the address ranges
Andreas Hansson
2013-01-07
config: Traverse lists when visiting children in all proxy
Andreas Hansson
2012-11-02
sim: Add drain methods to request additional cleanup operations
Andreas Sandberg
2012-11-02
sim: Add SWIG interface for Serializable
Andreas Sandberg
2012-11-02
python: Rename doDrain()->drain() and make it do the right thing
Andreas Sandberg
2012-11-02
sim: Reuse the code to change memory mode.
Andreas Sandberg
2012-11-02
sim: Move the draining interface into a separate base class
Andreas Sandberg
2012-11-02
sim: Include object header files in SWIG interfaces
Andreas Sandberg
2012-11-02
Partly revert [4f54b0f229b5] and move draining to m5.changeToTiming
Andreas Sandberg
2012-10-15
Param: Fix proxy traversal to support chained proxies
Andreas Hansson
2012-09-25
Statistics: Add a function to configure periodic stats dumping
Sascha Bischoff
2012-09-25
sim: Move CPU-specific methods from SimObject to the BaseCPU class
Andreas Sandberg
2012-09-25
sim: Remove SimObject::setMemoryMode
Andreas Sandberg
2012-09-19
AddrRange: Transition from Range<T> to AddrRange
Andreas Hansson
2012-09-19
AddrRange: Simplify AddrRange params Python hierarchy
Andreas Hansson
2012-09-12
Standard Switch: Drain the system before switching CPUs
Joel Hestness
2012-09-07
sim: Remove the unused SimObject::regFormulas method
Andreas Sandberg
2012-09-07
Param: Transition to Cycles for relevant parameters
Andreas Hansson
2012-08-28
Clock: Add a Cycles wrapper class and use where applicable
Andreas Hansson
2012-07-10
ruby: changes how Topologies are created
Brad Beckmann
2012-06-05
stats: Provide a mechanism to get a callback when stats are dumped.
Mitchell Hayenga
2012-05-23
Config: Use the attribute naming and include ports in JSON
Andreas Hansson
2012-05-23
Config: Exit with fatal if a port is already connected
Andreas Hansson
2012-05-10
DOT: improved dot-based system visualization
Uri Wiener
2012-05-10
DOT: fixed broken code for visualizing configuration using dot
Uri Wiener
2012-05-10
stats: track if the stats have been enabled and prevent requesting master id
Ali Saidi
2012-04-14
Regression: Add ANSI colours to highlight test status
Andreas Hansson
2012-04-06
python: added __nonzero__ function to SimObject Bool params
Brad Beckmann
2012-04-05
Python: Make the All proxy traverse SimObject children as well
Andreas Hansson
[next]