gem5 - gem5

Age	Commit message (Expand)	Author
2007-06-10	Add a function to get a SimObject's memory mode and rework	Nathan Binkert
2007-05-19	PhysicalMemory has vector of uniform ports instead of one special one.	Steve Reinhardt
2007-03-06	Move all of the parameters of the Root SimObject so they are	Nathan Binkert
2007-03-03	Do the default argument stuff in python	Nathan Binkert
2007-03-02	Factor code out of main.cc and main.i into a bunch of files	Nathan Binkert
2007-02-17	Get rid of the Statistics and Statreset ParamContexts, and	Nathan Binkert
2007-02-17	Pass an exception from a python event through the event queue	Nathan Binkert
2007-02-10	Clean up tracing stuff more, get rid of the trace log since	Nathan Binkert
2007-02-09	Get rid of the Random context and add the support directly to python.	Nathan Binkert
2007-02-09	Clean up from my last commit to the trace stuff.	Nathan Binkert
2007-02-09	Get rid of the Trace ParamContext and give python direct	Nathan Binkert
2006-12-21	Fix copyright	Nathan Binkert
2006-12-21	Expose the C++ event queue to python via the python function	Nathan Binkert
2006-12-21	move the swig initialization calls from src/sim/main.cc to	Nathan Binkert
2006-11-13	Expose debugBreakCycle through swig and get rid of	Nathan Binkert