gem5 - gem5

Age	Commit message (Expand)	Author
2013-10-31	config: Fix handling of parents for simobject vectors	Geoffrey Blake
2013-10-17	config: Fix ommission of number base in ethernet address param	Geoffrey Blake
2013-10-17	config: Fix for port references generated multiple times	Geoffrey Blake
2013-09-18	swig: Fix issue with circular import in 2.0.9/2.0.10	Andreas Hansson
2013-09-04	util: Add ini string as tooltip info in dot output	Andreas Hansson
2013-09-04	util: Add colours to the dot output	Andreas Hansson
2013-09-04	util: Add class name to dot graph and output to svg	Andreas Hansson
2013-09-04	arch: Resurrect the NOISA build target and rename it NULL	Andreas Hansson
2013-08-19	power: Add voltage domains to the clock domains	Akash Bagdia
2013-07-18	sim: Make MaxTick in Python match the one in C++	Andreas Hansson
2013-06-27	config: Remove Clock parameter multiplication	Andreas Hansson
2013-06-03	base: Make the Python module loader PEP302 compliant	Andreas Sandberg
2013-02-19	scons: Add warning for missing declarations	Andreas Hansson
2013-02-19	x86: Move APIC clock divider to Python	Andreas Hansson
2013-02-15	base: Add warn() and inform() to m5.utils for use from python	Sascha Bischoff
2013-02-15	sim: Add a system-global option to bypass caches	Andreas Sandberg
2013-02-15	config: Move CPU handover logic to m5.switchCpus()	Andreas Sandberg
2013-02-10	base: Add support for newer versions of IPython	Andreas Sandberg
2013-02-10	base: Fix broken IPython argument handling	Andreas Sandberg
2013-01-07	stats: Fix swig wrapping for Tick in stats	Sascha Bischoff
2013-01-07	cpu: Introduce sanity checks when switching between CPUs	Andreas Sandberg
2013-01-07	mem: Add interleaving bits to the address ranges	Andreas Hansson
2013-01-07	config: Traverse lists when visiting children in all proxy	Andreas Hansson
2012-11-16	sim: have a curTick per eventq	Nilay Vaish
2012-11-02	sim: Add drain methods to request additional cleanup operations	Andreas Sandberg
2012-11-02	sim: Add SWIG interface for Serializable	Andreas Sandberg
2012-11-02	python: Rename doDrain()->drain() and make it do the right thing	Andreas Sandberg
2012-11-02	sim: Reuse the code to change memory mode.	Andreas Sandberg
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-11-02	Partly revert [4f54b0f229b5] and move draining to m5.changeToTiming	Andreas Sandberg
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-10-15	Param: Fix proxy traversal to support chained proxies	Andreas Hansson
2012-09-25	Statistics: Add a function to configure periodic stats dumping	Sascha Bischoff
2012-09-25	sim: Move CPU-specific methods from SimObject to the BaseCPU class	Andreas Sandberg
2012-09-25	sim: Remove SimObject::setMemoryMode	Andreas Sandberg
2012-09-19	AddrRange: Transition from Range<T> to AddrRange	Andreas Hansson
2012-09-19	AddrRange: Simplify AddrRange params Python hierarchy	Andreas Hansson
2012-09-12	Standard Switch: Drain the system before switching CPUs	Joel Hestness
2012-09-07	sim: Remove the unused SimObject::regFormulas method	Andreas Sandberg
2012-09-07	Param: Transition to Cycles for relevant parameters	Andreas Hansson
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-07-10	ruby: changes how Topologies are created	Brad Beckmann
2012-06-05	sim: Remove FastAlloc	Ali Saidi
2012-06-05	stats: Provide a mechanism to get a callback when stats are dumped.	Mitchell Hayenga
2012-05-23	Config: Use the attribute naming and include ports in JSON	Andreas Hansson
2012-05-23	Config: Exit with fatal if a port is already connected	Andreas Hansson
2012-05-10	DOT: improved dot-based system visualization	Uri Wiener
2012-05-10	DOT: fixed broken code for visualizing configuration using dot	Uri Wiener
2012-05-10	stats: track if the stats have been enabled and prevent requesting master id	Ali Saidi