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2015-03-23misc: quote args in echoed command lineSteve Reinhardt
Currently if there are shell special characters in a command-line argument, you can't copy and paste the echoed command line onto a shell prompt because the characters aren't quoted properly. This patch fixes that problem.
2015-02-03base: Add XOR-based hashed address interleavingAndreas Hansson
This patch extends the current address interleaving with basic hashing support. Instead of directly comparing a number of address bits with a matching value, it is now possible to use two independent set of address bits XOR'ed together. This avoids issues where strided address patterns are heavily biased to a subset of the interleaved ranges.
2015-02-03config: Fix typo in Float paramGeoffrey Blake
The Float param was not settable on the command line due to a typo in the class definition in python/m5/params.py. This corrects the typo and allows floats to be set on the command line as intended.
2014-12-23sim: fix reference counting of PythonEventCurtis Dunham
When gem5 is a slave to another simulator and the Python is only used to initialize the configuration (and not perform actual simulation), a "debug start" (--debug-start) event will get freed during or immediately after the initial Python frame's execution rather than remaining in the event queue. This tricky patch fixes the GC issue causing this.
2014-12-02scons: Ensure dictionary iteration is sorted by keyAndreas Hansson
This patch adds sorting based on the SimObject name or parameter name for all situations where we iterate over dictionaries. This should ensure a deterministic and consistent order across the host systems and hopefully avoid regression results differing across python versions.
2014-11-12sim: Sort SimObject descendants and portsAndreas Hansson
This patch fixes a number of occurences where the sorting order of the objects was implementation defined.
2014-11-06ruby: interface with classic memory controllerNilay Vaish
This patch is the final in the series. The whole series and this patch in particular were written with the aim of interfacing ruby's directory controller with the memory controller in the classic memory system. This is being done since ruby's memory controller has not being kept up to date with the changes going on in DRAMs. Classic's memory controller is more up to date and supports multiple different types of DRAM. This also brings classic and ruby ever more close. The patch also changes ruby's memory controller to expose the same interface.
2014-10-16sim: EventQueue wakeup on events scheduled outside the event loopAndreas Hansson
This patch adds a 'wakeup' member function to EventQueue which should be called on an event queue whenever an event is scheduled on the event queue from outside code within the call tree of the gem5 event loop. This clearly isn't necessary for normal gem5 EventQueue operation but becomes the minimum necessary interface to allow hosting gem5's event loop onto other schedulers where there may be calls into gem5 from external code which schedules events onto an EventQueue between the current time and the time of the next scheduled event. The use case I have in mind is a SystemC hosting where the event loop is: while (more events) { wait(time_to_next_event or wakeup) setCurTick service events at this time } where the 'wait' needs to be woken up if time_to_next_event becomes shorter due to a scheduled event from SystemC arriving in a gem5 object. Requiring 'wakeup' to be called is a more efficient interface than requiring all gem5 event scheduling actions to affect the host scheduler. This interface could be located elsewhere, say on another global object, or by being passed by the host scheduler to objects which will schedule such events, but it seems cleanest to put it on EventQueue as it is actually a signal to the queue. EventQueue::wakeup is called for async_event events on event queue 0 as it's only important that *some* queue be triggered for such events.
2014-10-16base: Reimplement the DPRINTF mechanism in a Logger classAndrew Bardsley
This patch adds a Logger class encapsulating dprintf. This allows variants of DPRINTF logging to be constructed and substituted in place of the default behaviour. The Logger provides a logMessage(when, name, format, ...) member function like Trace::dprintf and a getOstream member function to use a raw ostream for logging. A class OstreamLogger is provided which generates the customary debugging output with Trace::OstreamLogger::logMessage being the old Trace::dprintf.
2014-10-16config: Add the ability to read a config file using C++ and PythonAndreas Hansson
This patch adds the ability to load in config.ini files generated from gem5 into another instance of gem5 built without Python configuration support. The intended use case is for configuring gem5 when it is a library embedded in another simulation system. A parallel config file reader is also provided purely in Python to demonstrate the approach taken and to provided similar functionality for as-yet-unknown use models. The Python configuration file reader can read both .ini and .json files. C++ configuration file reading: A command line option has been added for scons to enable C++ configuration file reading: --with-cxx-config There is an example in util/cxx_config that shows C++ configuration in action. util/cxx_config/README explains how to build the example. Configuration is achieved by the object CxxConfigManager. It handles reading object descriptions from a CxxConfigFileBase object which wraps a config file reader. The wrapper class CxxIniFile is provided which wraps an IniFile for reading .ini files. Reading .json files from C++ would be possible with a similar wrapper and a JSON parser. After reading object descriptions, CxxConfigManager creates SimObjectParam-derived objects from the classes in the (generated with this patch) directory build/ARCH/cxx_config CxxConfigManager can then build SimObjects from those SimObjectParams (in an order dictated by the SimObject-value parameters on other objects) and bind ports of the produced SimObjects. A minimal set of instantiate-replacing member functions are provided by CxxConfigManager and few of the member functions of SimObject (such as drain) are extended onto CxxConfigManager. Python configuration file reading (configs/example/read_config.py): A Python version of the reader is also supplied with a similar interface to CxxConfigFileBase (In Python: ConfigFile) to config file readers. The Python config file reading will handle both .ini and .json files. The object construction strategy is slightly different in Python from the C++ reader as you need to avoid objects prematurely becoming the children of other objects when setting parameters. Port binding also needs to be strictly in the same port-index order as the original instantiation.
2014-10-16config: Add a --without-python option to build processAndrew Bardsley
Add the ability to build libgem5 without embedded Python or the ability to configure with Python. This is a prelude to a patch to allow config.ini files to be loaded into libgem5 using only C++ which would make embedding gem5 within other simulation systems easier. This adds a few registration interfaces to things which cross between Python and C++. Namely: stats dumping and SimObject resolving
2014-10-11sim: draining bug for fast-forwaring multiple coresAndrew Lukefahr
fix draining bug where multiple cores hit max_insts_any_thread simultaneously Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-10-09config: Add Current as a parameter typeAndreas Hansson
This patch adds the Python parameter type Current, which is used for the DRAM power modelling (to start with). With this addition we avoid implicit unit assumptions.
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus. As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet. --HG-- rename : src/mem/Bus.py => src/mem/XBar.py rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh rename : src/mem/bus.cc => src/mem/xbar.cc rename : src/mem/bus.hh => src/mem/xbar.hh
2014-09-20config: Cleanup .json config file generationAndrew Bardsley
This patch 'completes' .json config files generation by adding in the SimObject references and String-valued parameters not currently printed. TickParamValues are also changed to print in the same tick-value format as in .ini files. This allows .json files to describe a system as fully as the .ini files currently do. This patch adds a new function config_value (which mirrors ini_str) to each ParamValue and to SimObject. This function can then be explicitly changed to give different .json and .ini printing behaviour rather than being written in terms of ini_str.
2014-09-09config: Fix vectorparam command line parsingGeoffrey Blake
Parsing vectorparams from the command was slightly broken in that it wouldn't accept the input that the help message provided to the user and it didn't do the conversion on the second code path used to convert the string input to the actual internal representation. This patch fixes these bugs.
2014-09-03config: Add port splicing capability to PortRef classGeoffrey Blake
The new configuration scripts need the ability to splice a simobject between a pair of ports that are already connected. The primary use case is when a CommMonitor needs to be created after the system is configured and then spliced between the pair of ports it will monitor.
2014-09-03config: Change parsing of Addr so hex values work from scriptsMitch Hayenga
When passed from a configuration script with a hexadecimal value (like "0x80000000"), gem5 would error out. This is because it would call "toMemorySize" which requires the argument to end with a size specifier (like 1MB, etc). This modification makes it so raw hex values can be passed through Addr parameters from the configuration scripts.
2014-09-01ruby: message buffers: significant changesNilay Vaish
This patch is the final patch in a series of patches. The aim of the series is to make ruby more configurable than it was. More specifically, the connections between controllers are not at all possible (unless one is ready to make significant changes to the coherence protocol). Moreover the buffers themselves are magically connected to the network inside the slicc code. These connections are not part of the configuration file. This patch makes changes so that these connections will now be made in the python configuration files associated with the protocols. This requires each state machine to expose the message buffers it uses for input and output. So, the patch makes these buffers configurable members of the machines. The patch drops the slicc code that usd to connect these buffers to the network. Now these buffers are exposed to the python configuration system as Master and Slave ports. In the configuration files, any master port can be connected any slave port. The file pyobject.cc has been modified to take care of allocating the actual message buffer. This is inline with how other port connections work.
2014-08-10config: Add hooks to enable new config sysGeoffrey Blake
This patch adds helper functions to SimObject.py, params.py and simulate.py to enable the new configuration system. Functions like enumerateParams() in SimObject lets the config system auto-generate command line options for simobjects to be modified on the command line. Params in params.py have __call__() added to their definition to allow the argparse module to use them as a type to check command input is in the proper format.
2014-05-09cpu: Add flag name printing to StaticInstAndrew Bardsley
This patch adds a the member function StaticInst::printFlags to allow all of an instruction's flags to be printed without using the individual is... member functions or resorting to exposing the 'flags' vector It also replaces the enum definition StaticInst::Flags with a Python-generated enumeration and adds to the enum generation mechanism in src/python/m5/params.py to allow Enums to be placed in namespaces other than Enums or, alternatively, in wrapper structs allowing them to be inherited by other classes (so populating that class's name-space with the enumeration element names).
2014-05-09config: Avoid generating a reference to myself for Parent.anyGeoffrey Blake
The unproxy code for Parent.any can generate a circular reference in certain situations with classes hierarchies like those in ClockDomain.py. This patch solves this by marking ouself as visited to make sure the search does not resolve to a self-reference.
2014-05-09scons: Require SWIG >= 2.0.4 and remove vector typemapsCurtis Dunham
SWIG commit fd666c1 (*) made it unnecessary for gem5 to have these typemaps to handle Vector types. * https://github.com/swig/swig/commit/fd666c1440628a847793bbe1333c27dfa2f757f0
2014-04-23misc: Proper type check and import for PortRefSascha Bischoff
Rewriting the type checking around PortRef, which was interacting strangely with other Python scripts. Tested-by: stephan.diestelhorst@arm.com
2014-02-10stats: better error message for uninitialized statisticCurtis Dunham
As suggested by Nathan Binkert in 2008: http://permalink.gmane.org/gmane.comp.emulators.m5.users/2676
2014-03-23misc: Fix -q (quiet) flagStan Czerniawski
Check the right flag.
2014-01-24base: add support for probe points and common probesMatt Horsnell
The probe patch is motivated by the desire to move analytical and trace code away from functional code. This is achieved by the probe interface which is essentially a glorified observer model. What this means to users: * add a probe point and a "notify" call at the source of an "event" * add an isolated module, that is being used to carry out *your* analysis (e.g. generate a trace) * register that module as a probe listener Note: an example is given for reference in src/cpu/o3/simple_trace.[hh|cc] and src/cpu/SimpleTrace.py What is happening under the hood: * every SimObject maintains has a ProbeManager. * during initialization (src/python/m5/simulate.py) first regProbePoints and the regProbeListeners is called on each SimObject. this hooks up the probe point notify calls with the listeners. FAQs: Why did you develop probe points: * to remove trace, stats gathering, analytical code out of the functional code. * the belief that probes could be generically useful. What is a probe point: * a probe point is used to notify upon a given event (e.g. cpu commits an instruction) What is a probe listener: * a class that handles whatever the user wishes to do when they are notified about an event. What can be passed on notify: * probe points are templates, and so the user can generate probes that pass any type of argument (by const reference) to a listener. What relationships can be generated (1:1, 1:N, N:M etc): * there isn't a restriction. You can hook probe points and listeners up in a 1:1, 1:N, N:M relationship. They become useful when a number of modules listen to the same probe points. The idea being that you can add a small number of probes into the source code and develop a larger number of useful analysis modules that use information passed by the probes. Can you give examples: * adding a probe point to the cpu's commit method allows you to build a trace module (outputting assembler), you could re-use this to gather instruction distribution (arithmetic, load/store, conditional, control flow) stats. Why is the probe interface currently restricted to passing a const reference: * the desire, initially at least, is to allow an interface to observe functionality, but not to change functionality. * of course this can be subverted by const-casting. What is the performance impact of adding probes: * when nothing is actively listening to the probes they should have a relatively minor impact. Profiling has suggested even with a large number of probes (60) the impact of them (when not active) is very minimal (<1%).
2014-01-24config: Make the Clock a Tick parameter like Latency/FrequencyAndreas Hansson
This patch makes the Clock a TickParamValue just like Latency/Frequency. There is no longer any need to distinguish it (originally needed to support multiplication).
2014-01-03python: provide better error message for wrapped C++ methodsSteve Reinhardt
If you successfully export a C++ SimObject method, but try to invoke it from Python before the C++ object is created, you get a confusing error that says the attribute does not exist, making you question whether you successfully exported the method at all. In reality, your only problem is that you're calling the method too soon. This patch enhances the error message to give you a better clue.
2014-01-03python: don't die on assignment to cloned objectSteve Reinhardt
Updating the SimObject topology of a cloned hierarchy is a little dangerous, in that cloning is a "deep copy" and the clone does not inherit SimObject updates the same way it would inherit scalar variable assignments. However, because of various SimObject-valued proxy parameters, like 'memories', 'clk_domain', and 'system', it turns out that there are a number of implicit topology changes that happen at instantiation, which means that these changes are impossible to avoid. So in order to make cloning systems useful, this error has to go. Changing it to a warning produces a lot of noise, so it seems best just to delete it.
2013-12-03sim: reset stats after startupNilay Vaish
Currently statistics are reset after the initial / checkpoint state has been loaded. But ruby does some checkpoint processing in its startup() function. So the stats need to be reset after the startup() function has been called. This patch moves the class to stats.reset() to achieve this change in functionality.
2013-11-25sim: simulate with multiple threads and event queuesSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
This patch adds support for simulating with multiple threads, each of which operates on an event queue. Each sim object specifies which eventq is would like to be on. A custom barrier implementation is being added using which eventqs synchronize. The patch was tested in two different configurations: 1. ruby_network_test.py: in this simulation L1 cache controllers receive requests from the cpu. The requests are replied to immediately without any communication taking place with any other level. 2. twosys-tsunami-simple-atomic: this configuration simulates a client-server system which are connected by an ethernet link. We still lack the ability to communicate using message buffers or ports. But other things like simulation start and end, synchronizing after every quantum are working. Committed by: Nilay Vaish
2013-11-14tests: suppress output on switcheroo testsSteve Reinhardt
The output from the switcheroo tests is voluminous and (because it includes timestamps) highly sensitive to minor changes, leading to extremely large updates to the reference outputs. This patch addresses this problem by suppressing output from the tests. An internal parameter can be set to enable the output. Wiring that up to a command-line flag (perhaps even the rudimantary -v/-q options in m5/main.py) is left for future work.
2013-11-01sim: Clarify the difference between tracing and debuggingAndreas Hansson
This patch changes the name the command-line options related to debug output to all start with "debug" rather than being a mix of that and "trace". It also makes it clear that the breakpoint time is specified in ticks and not in cycles.
2013-10-31config: Fix handling of parents for simobject vectorsGeoffrey Blake
SimObjectVector objects did not provide the same interface to the _parent attribute through get_parent() like a normal SimObject. It also handled assigning a _parent incorrectly if objects in a SimObjectVector were changed post-creation, leading to errors later when the simulator tried to execute. This patch fixes these two omissions.
2013-10-17config: Fix ommission of number base in ethernet address paramGeoffrey Blake
The ethernet address param tries to convert a hexadecimal string using int() in python, which defaults to base 10, need to specify base 16 in this case.
2013-10-17config: Fix for port references generated multiple timesGeoffrey Blake
SimObjects are expected to only generate one port reference per port belonging to them. There is a subtle bug with using "not" here as a VectorPort is seen as not having a reference if it is either None or empty as per Python docs sec 9.9 for Standard operators. Intended behavior is to only check if we have not created the reference.
2013-09-18swig: Fix issue with circular import in 2.0.9/2.0.10Andreas Hansson
This patch fixes an issue which prevented gem5 from running when built using swig 2.0.9 and 2.0.10. The generated event.py tried to import m5.internal which in turn relied on importing event. This patch seems to fix the problem, and so far has not caused any other issues.
2013-09-04util: Add ini string as tooltip info in dot outputAndreas Hansson
This patch adds the config ini string as a tooltip that can be displayed in most browsers rendering the resulting svg. Certain characters are modified for HTML output. Tested on chrome and firefox.
2013-09-04util: Add colours to the dot outputAndreas Hansson
This patch is adding a splash of colour to the dot output to make it easier to distinguish objects of different types. As a bonus, the pastel-colour palette also makes the output look like a something from the 21st century.
2013-09-04util: Add class name to dot graph and output to svgAndreas Hansson
This patch adds the class name to the label, creates some more space by increasing the rank separation, and additionally outputs the graph as an editable SVG in addition to the PDF.
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
This patch makes it possible to once again build gem5 without any ISA. The main purpose is to enable work around the interconnect and memory system without having to build any CPU models or device models. The regress script is updated to include the NULL ISA target. Currently no regressions make use of it, but all the testers could (and perhaps should) transition to it. --HG-- rename : build_opts/NOISA => build_opts/NULL rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
This patch adds the notion of voltage domains, and groups clock domains that operate under the same voltage (i.e. power supply) into domains. Each clock domain is required to be associated with a voltage domain, and the latter requires the voltage to be explicitly set. A voltage domain is an independently controllable voltage supply being provided to section of the design. Thus, if you wish to perform dynamic voltage scaling on a CPU, its clock domain should be associated with a separate voltage domain. The current implementation of the voltage domain does not take into consideration cases where there are derived voltage domains running at ratio of native voltage domains, as with the case where there can be on-chip buck/boost (charge pumps) voltage regulation logic. The regression and configuration scripts are updated with a generic voltage domain for the system, and one for the CPUs.
2013-07-18sim: Make MaxTick in Python match the one in C++Andreas Hansson
This patch aligns the MaxTick in Python with the one in C++. Thus, both reflect the maximum value that an unsigned 64-bit integer can have.
2013-06-27config: Remove Clock parameter multiplicationAndreas Hansson
This patch removes the multiplication operator support for Clock parameters as this functionality is now achieved by creating derived clock domains. Nate, this one is for you.
2013-06-03base: Make the Python module loader PEP302 compliantAndreas Sandberg
The custom Python loader didn't comply with PEP302 for two reasons: * Previously, we would overwrite old modules on name conflicts. PEP302 explicitly states that: "If there is an existing module object named 'fullname' in sys.modules, the loader must use that existing module". * The "__package__" attribute wasn't set. PEP302: "The __package__ attribute must be set." This changeset addresses both of these issues.
2013-02-19scons: Add warning for missing declarationsAndreas Hansson
This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code.
2013-02-19x86: Move APIC clock divider to PythonAndreas Hansson
This patch moves the 16x APIC clock divider to the Python code to avoid the post-instantiation modifications to the clock. The x86 APIC was the only object setting the clock after creation time and this required some custom functionality and configuration. With this patch, the clock multiplier is moved to the Python code and the objects are instantiated with the appropriate clock.
2013-02-15base: Add warn() and inform() to m5.utils for use from pythonSascha Bischoff
This patch adds two fuctions to m5.util, warn and inform, which mirror those found in the C++ side of gem5. These are added in addition to the already existing m5.util.panic and m5.util.fatal which already mirror the C++ functionality. This ensures that warning and information messages generated by python are in the same format as those generated by C++. Occurrences of print "Warning: %s..." % name have been replaced with warn("%s...", name)
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
Virtualized CPUs and the fastmem mode of the atomic CPU require direct access to physical memory. We currently require caches to be disabled when using them to prevent chaos. This is not ideal when switching between hardware virutalized CPUs and other CPU models as it would require a configuration change on each switch. This changeset introduces a new version of the atomic memory mode, 'atomic_noncaching', where memory accesses are inserted into the memory system as atomic accesses, but bypass caches. To make memory mode tests cleaner, the following methods are added to the System class: * isAtomicMode() -- True if the memory mode is 'atomic' or 'direct'. * isTimingMode() -- True if the memory mode is 'timing'. * bypassCaches() -- True if caches should be bypassed. The old getMemoryMode() and setMemoryMode() methods should never be used from the C++ world anymore.