gem5 - gem5

Age	Commit message (Expand)	Author
2017-01-03	python: Don't use Swig to cast stats	Andreas Sandberg
2017-01-03	sim: Remove redundant export_method_cxx_predecls	Andreas Sandberg
2016-12-19	python: Export periodicStatDump	Andreas Sandberg
2016-09-15	base: eliminate ipython warning	Curtis Dunham
2016-09-13	misc: Remove FullSystem check for networking components	Michael LeBeane
2016-09-13	base: Output all AddrRange parameters to config.ini	Matt Poremba
2016-05-27	power: Allow voltage to be configured via cmd line	Akash Bagdia
2016-04-06	misc: Bail out of DVFS dot if we cannot resolve the domains	Sascha Bischoff
2015-12-15	misc: Add secondary dot output for DVFS domains	Sascha Bischoff
2016-03-30	misc: Don't build region.py as a PySource	Andreas Sandberg
2016-03-30	style: Refactor the style checker as a Python package	Andreas Sandberg
2015-11-26	sim: Add support for forking	Andreas Sandberg
2015-11-26	sim: Add support for notifying Drainable objects of a fork	Andreas Sandberg
2015-11-27	base: Add support for changing output directories	Andreas Sandberg
2016-02-13	configs: add command-line option to stop debug output	Michael LeBeane
2016-02-06	style: fix missing spaces in control statements	Steve Reinhardt
2016-02-06	style: remove trailing whitespace	Steve Reinhardt
2016-01-17	sim: fix redundant --debug-start help string	Steve Reinhardt
2016-01-17	sim: don't ignore SIG_TRAP	Steve Reinhardt
2015-12-10	dev: Move network devices to src/dev/net/	Andreas Sandberg
2015-12-01	config: Fix broken SimObject listing	Andreas Sandberg
2015-11-22	config: Added missing types to JSON/INI Python reader	Andrew Bardsley
2015-10-06	sim: print pid in output header	Steve Reinhardt
2015-09-30	base: remove Trace::enabled flag	Curtis Dunham
2015-08-14	ruby: Expose MessageBuffers as SimObjects	Joel Hestness
2015-07-07	sim: Decouple draining from the SimObject hierarchy	Andreas Sandberg
2015-07-07	sim: Move mem(Writeback\|Invalidate) to SimObject	Andreas Sandberg
2015-07-07	python: Remove redundant drain when changing memory modes	Andreas Sandberg
2015-07-07	sim: Refactor the serialization base class	Andreas Sandberg
2015-03-23	misc: quote args in echoed command line	Steve Reinhardt
2015-02-03	base: Add XOR-based hashed address interleaving	Andreas Hansson
2015-02-03	config: Fix typo in Float param	Geoffrey Blake
2014-12-23	sim: fix reference counting of PythonEvent	Curtis Dunham
2014-12-02	scons: Ensure dictionary iteration is sorted by key	Andreas Hansson
2014-11-12	sim: Sort SimObject descendants and ports	Andreas Hansson
2014-11-06	ruby: interface with classic memory controller	Nilay Vaish
2014-10-16	sim: EventQueue wakeup on events scheduled outside the event loop	Andreas Hansson
2014-10-16	base: Reimplement the DPRINTF mechanism in a Logger class	Andrew Bardsley
2014-10-16	config: Add the ability to read a config file using C++ and Python	Andreas Hansson
2014-10-16	config: Add a --without-python option to build process	Andrew Bardsley
2014-10-11	sim: draining bug for fast-forwaring multiple cores	Andrew Lukefahr
2014-10-09	config: Add Current as a parameter type	Andreas Hansson
2014-09-20	mem: Rename Bus to XBar to better reflect its behaviour	Andreas Hansson
2014-09-20	config: Cleanup .json config file generation	Andrew Bardsley
2014-09-09	config: Fix vectorparam command line parsing	Geoffrey Blake
2014-09-03	config: Add port splicing capability to PortRef class	Geoffrey Blake
2014-09-03	config: Change parsing of Addr so hex values work from scripts	Mitch Hayenga
2014-09-01	ruby: message buffers: significant changes	Nilay Vaish
2014-08-10	config: Add hooks to enable new config sys	Geoffrey Blake
2014-05-09	cpu: Add flag name printing to StaticInst	Andrew Bardsley