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AgeCommit message (Expand)Author
2014-01-03python: provide better error message for wrapped C++ methodsSteve Reinhardt
2014-01-03python: don't die on assignment to cloned objectSteve Reinhardt
2013-12-03sim: reset stats after startupNilay Vaish
2013-11-25sim: simulate with multiple threads and event queuesSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2013-11-14tests: suppress output on switcheroo testsSteve Reinhardt
2013-11-01sim: Clarify the difference between tracing and debuggingAndreas Hansson
2013-10-31config: Fix handling of parents for simobject vectorsGeoffrey Blake
2013-10-17config: Fix ommission of number base in ethernet address paramGeoffrey Blake
2013-10-17config: Fix for port references generated multiple timesGeoffrey Blake
2013-09-18swig: Fix issue with circular import in 2.0.9/2.0.10Andreas Hansson
2013-09-04util: Add ini string as tooltip info in dot outputAndreas Hansson
2013-09-04util: Add colours to the dot outputAndreas Hansson
2013-09-04util: Add class name to dot graph and output to svgAndreas Hansson
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
2013-07-18sim: Make MaxTick in Python match the one in C++Andreas Hansson
2013-06-27config: Remove Clock parameter multiplicationAndreas Hansson
2013-06-03base: Make the Python module loader PEP302 compliantAndreas Sandberg
2013-02-19scons: Add warning for missing declarationsAndreas Hansson
2013-02-19x86: Move APIC clock divider to PythonAndreas Hansson
2013-02-15base: Add warn() and inform() to m5.utils for use from pythonSascha Bischoff
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-02-15config: Move CPU handover logic to m5.switchCpus()Andreas Sandberg
2013-02-10base: Add support for newer versions of IPythonAndreas Sandberg
2013-02-10base: Fix broken IPython argument handlingAndreas Sandberg
2013-01-07stats: Fix swig wrapping for Tick in statsSascha Bischoff
2013-01-07cpu: Introduce sanity checks when switching between CPUsAndreas Sandberg
2013-01-07mem: Add interleaving bits to the address rangesAndreas Hansson
2013-01-07config: Traverse lists when visiting children in all proxyAndreas Hansson
2012-11-16sim: have a curTick per eventqNilay Vaish
2012-11-02sim: Add drain methods to request additional cleanup operationsAndreas Sandberg
2012-11-02sim: Add SWIG interface for SerializableAndreas Sandberg
2012-11-02python: Rename doDrain()->drain() and make it do the right thingAndreas Sandberg
2012-11-02sim: Reuse the code to change memory mode.Andreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-11-02Partly revert [4f54b0f229b5] and move draining to m5.changeToTimingAndreas Sandberg
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-10-15Param: Fix proxy traversal to support chained proxiesAndreas Hansson
2012-09-25Statistics: Add a function to configure periodic stats dumpingSascha Bischoff
2012-09-25sim: Move CPU-specific methods from SimObject to the BaseCPU classAndreas Sandberg
2012-09-25sim: Remove SimObject::setMemoryModeAndreas Sandberg
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
2012-09-19AddrRange: Simplify AddrRange params Python hierarchyAndreas Hansson
2012-09-12Standard Switch: Drain the system before switching CPUsJoel Hestness
2012-09-07sim: Remove the unused SimObject::regFormulas methodAndreas Sandberg
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-07-10ruby: changes how Topologies are createdBrad Beckmann
2012-06-05sim: Remove FastAllocAli Saidi
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