gem5 - gem5

Age	Commit message (Expand)	Author
2015-07-07	sim: Move mem(Writeback\|Invalidate) to SimObject	Andreas Sandberg
2015-07-07	python: Remove redundant drain when changing memory modes	Andreas Sandberg
2015-07-07	sim: Refactor the serialization base class	Andreas Sandberg
2015-03-23	misc: quote args in echoed command line	Steve Reinhardt
2015-02-03	base: Add XOR-based hashed address interleaving	Andreas Hansson
2015-02-03	config: Fix typo in Float param	Geoffrey Blake
2014-12-23	sim: fix reference counting of PythonEvent	Curtis Dunham
2014-12-02	scons: Ensure dictionary iteration is sorted by key	Andreas Hansson
2014-11-12	sim: Sort SimObject descendants and ports	Andreas Hansson
2014-11-06	ruby: interface with classic memory controller	Nilay Vaish
2014-10-16	sim: EventQueue wakeup on events scheduled outside the event loop	Andreas Hansson
2014-10-16	base: Reimplement the DPRINTF mechanism in a Logger class	Andrew Bardsley
2014-10-16	config: Add the ability to read a config file using C++ and Python	Andreas Hansson
2014-10-16	config: Add a --without-python option to build process	Andrew Bardsley
2014-10-11	sim: draining bug for fast-forwaring multiple cores	Andrew Lukefahr
2014-10-09	config: Add Current as a parameter type	Andreas Hansson
2014-09-20	mem: Rename Bus to XBar to better reflect its behaviour	Andreas Hansson
2014-09-20	config: Cleanup .json config file generation	Andrew Bardsley
2014-09-09	config: Fix vectorparam command line parsing	Geoffrey Blake
2014-09-03	config: Add port splicing capability to PortRef class	Geoffrey Blake
2014-09-03	config: Change parsing of Addr so hex values work from scripts	Mitch Hayenga
2014-09-01	ruby: message buffers: significant changes	Nilay Vaish
2014-08-10	config: Add hooks to enable new config sys	Geoffrey Blake
2014-05-09	cpu: Add flag name printing to StaticInst	Andrew Bardsley
2014-05-09	config: Avoid generating a reference to myself for Parent.any	Geoffrey Blake
2014-05-09	scons: Require SWIG >= 2.0.4 and remove vector typemaps	Curtis Dunham
2014-04-23	misc: Proper type check and import for PortRef	Sascha Bischoff
2014-02-10	stats: better error message for uninitialized statistic	Curtis Dunham
2014-03-23	misc: Fix -q (quiet) flag	Stan Czerniawski
2014-01-24	base: add support for probe points and common probes	Matt Horsnell
2014-01-24	config: Make the Clock a Tick parameter like Latency/Frequency	Andreas Hansson
2014-01-03	python: provide better error message for wrapped C++ methods	Steve Reinhardt
2014-01-03	python: don't die on assignment to cloned object	Steve Reinhardt
2013-12-03	sim: reset stats after startup	Nilay Vaish
2013-11-25	sim: simulate with multiple threads and event queues	Steve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2013-11-14	tests: suppress output on switcheroo tests	Steve Reinhardt
2013-11-01	sim: Clarify the difference between tracing and debugging	Andreas Hansson
2013-10-31	config: Fix handling of parents for simobject vectors	Geoffrey Blake
2013-10-17	config: Fix ommission of number base in ethernet address param	Geoffrey Blake
2013-10-17	config: Fix for port references generated multiple times	Geoffrey Blake
2013-09-18	swig: Fix issue with circular import in 2.0.9/2.0.10	Andreas Hansson
2013-09-04	util: Add ini string as tooltip info in dot output	Andreas Hansson
2013-09-04	util: Add colours to the dot output	Andreas Hansson
2013-09-04	util: Add class name to dot graph and output to svg	Andreas Hansson
2013-09-04	arch: Resurrect the NOISA build target and rename it NULL	Andreas Hansson
2013-08-19	power: Add voltage domains to the clock domains	Akash Bagdia
2013-07-18	sim: Make MaxTick in Python match the one in C++	Andreas Hansson
2013-06-27	config: Remove Clock parameter multiplication	Andreas Hansson
2013-06-03	base: Make the Python module loader PEP302 compliant	Andreas Sandberg
2013-02-19	scons: Add warning for missing declarations	Andreas Hansson