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AgeCommit message (Expand)Author
2013-02-10base: Add support for newer versions of IPythonAndreas Sandberg
2013-02-10base: Fix broken IPython argument handlingAndreas Sandberg
2013-01-07stats: Fix swig wrapping for Tick in statsSascha Bischoff
2013-01-07cpu: Introduce sanity checks when switching between CPUsAndreas Sandberg
2013-01-07mem: Add interleaving bits to the address rangesAndreas Hansson
2013-01-07config: Traverse lists when visiting children in all proxyAndreas Hansson
2012-11-16sim: have a curTick per eventqNilay Vaish
2012-11-02sim: Add drain methods to request additional cleanup operationsAndreas Sandberg
2012-11-02sim: Add SWIG interface for SerializableAndreas Sandberg
2012-11-02python: Rename doDrain()->drain() and make it do the right thingAndreas Sandberg
2012-11-02sim: Reuse the code to change memory mode.Andreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-11-02Partly revert [4f54b0f229b5] and move draining to m5.changeToTimingAndreas Sandberg
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-10-15Param: Fix proxy traversal to support chained proxiesAndreas Hansson
2012-09-25Statistics: Add a function to configure periodic stats dumpingSascha Bischoff
2012-09-25sim: Move CPU-specific methods from SimObject to the BaseCPU classAndreas Sandberg
2012-09-25sim: Remove SimObject::setMemoryModeAndreas Sandberg
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
2012-09-19AddrRange: Simplify AddrRange params Python hierarchyAndreas Hansson
2012-09-12Standard Switch: Drain the system before switching CPUsJoel Hestness
2012-09-07sim: Remove the unused SimObject::regFormulas methodAndreas Sandberg
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-07-10ruby: changes how Topologies are createdBrad Beckmann
2012-06-05sim: Remove FastAllocAli Saidi
2012-06-05stats: Provide a mechanism to get a callback when stats are dumped.Mitchell Hayenga
2012-05-23Config: Use the attribute naming and include ports in JSONAndreas Hansson
2012-05-23Config: Exit with fatal if a port is already connectedAndreas Hansson
2012-05-10DOT: improved dot-based system visualizationUri Wiener
2012-05-10DOT: fixed broken code for visualizing configuration using dotUri Wiener
2012-05-10stats: track if the stats have been enabled and prevent requesting master idAli Saidi
2012-04-14Regression: Add ANSI colours to highlight test statusAndreas Hansson
2012-04-06python: added __nonzero__ function to SimObject Bool paramsBrad Beckmann
2012-04-05Python: Make the All proxy traverse SimObject children as wellAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-21Python: Fix a conditional expression that requires Python 2.5Andreas Hansson
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2012-03-19scripts: Fix to ensure that port connection count is always setAndreas Hansson
2012-02-29SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1Andreas Hansson
2012-02-20SimObject: make get_config_as_dict() tolerate undefined paramsSteve Reinhardt
2012-02-13MEM: Pass the ports from Python to C++ using the Swig paramsAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2012-01-28Merge with the main repo.Gabe Black
2012-01-16Merge yet again with the main repository.Gabe Black
2012-01-17MEM: Removing the default port peer from Python portsAndreas Hansson
2012-01-10Automated merge with ssh://repo.gem5.org/gem5Ali Saidi
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