Age | Commit message (Collapse) | Author |
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : fd6464c9883783c7c2cbefba317f4a0f20dd24cb
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configs/common/FSConfig.py:
add an attachOnChipIO to force people to think about where "onchip" i/o should be connected in their hierarchy
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extra : convert_revision : cf79a9a00760b7daf28063f407a04bd38b956843
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configs/common/FSConfig.py:
Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Add InterruptVector type
src/arch/sparc/interrupts.hh:
rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
Add checkSoftInt to check if a softint needs to be posted
Check that a tickCompare isn't scheduled before scheduling one
Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
update config.ini/out for intrcntrl not having a cpu pointer anymore
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so things are organized in a more sensible manner. Take apart
finalInit and expose the individual functions which are now
called from python. Make checkpointing a bit easier to use.
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extra : convert_revision : f470ddabbb47103e7b4734ef753c40089f2dcd9d
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relevant code directly into the SimConsole object. Now,
you can easily turn off the listen port by just specifying
0 as the port.
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extra : convert_revision : c8937fa45b429d8a0728e6c720a599e38972aaf0
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specified.
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extra : convert_revision : 49c1ea0b8c313949124aed84b1055db0b3c55bd8
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based on the swig modules that we have
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relevant stuff has now been moved to python.
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since they're no longer used
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extra : convert_revision : e39590aa03cc4c961d2eb5dab57862811f431e4d
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expose all of the relevant functionality to python. Clean
up the mysql code while we're at it.
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extra : convert_revision : 5b711202a5a452b8875ebefb136a156b65c24279
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on in python. Fix the trace start code so it actually starts
when it is suppsed to. Make the Exec tracing stuff obey the
trace enabled flag.
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extra : convert_revision : 634ba0b4f52345d4bf40d43e239cef7ef43e7691
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back into python so we don't just silently ignore those errors
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extra : convert_revision : e2f5566a4681f1b8ea80af50071119118afa7d8a
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src/dev/alpha/tsunamireg.h:
get rid of things that aren't really tsunami registers
src/dev/platform.hh:
src/dev/uart.cc:
the uart pointer isn't used anymore
src/dev/simconsole.cc:
make the simconsole print something more useful to distinguish between various consoles in a single system
src/dev/uart8250.hh:
put the needed uart defines in here rather than including them from tsunamireg
src/python/m5/objects/T1000.py:
add a console to the T1000 config for the hypervisor
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extra : convert_revision : 76ca92122e611eaf76b989bc699582eef8297be8
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the traceflags infrastructure. InstExec is now just Exec
and all of the command line options are now trace options.
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extra : convert_revision : 4adfa9dfbb32622d30ef4e63c06c7d87da793c8f
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the script is invoked as main. This allows us to import traceflags.py
if we just want the list of available flags.
Embed traceflags.py into the zipfile so it can be accessed from the
python side of things. With this, print an error on invalid flags and
add --trace-help option that will print out the list of trace flags
that are compiled in. If a flag is prefixed with a '-', now that flag
will be disabled.
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extra : convert_revision : 2260a596b07d127c582ff73474dbbdb0583db524
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its not all that useful. Fix a few bugs with python/C++
integration.
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We don't currently use randomness much, so I didn't go too far, but
in the future, we may want to actually expose the random number values
themselves to python. For now, I'll at least let you seed it.
While we're at it, clean up a clearly bad way for generating random
doubles.
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access to enabling/disabling tracing. Command line is
unchanged except for the removal of --trace-cycle since
it's not so clear what that means.
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extra : convert_revision : c0164d92d3615d76d0c6acaabaafd92a9278212a
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src/SConscript:
strip doesn't take a src and dest in solaris
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extra : convert_revision : 9398362237443dc659f423a342bd27c923e90aea
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pass the tuple of python's struct_time and interpret that.
Fixes a problem where the local timezone leaked into the time
calculation. Also fix things so that the unix, python, and RTC
data sheets all get the right time. Provide both years since 1900
and BCD two digit year.
Put the date back at 1/1/2006 for now.
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extra : convert_revision : 52e51ff49f7ed73065f04707ded06dc7254292c4
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configs/common/FSConfig.py:
src/python/m5/objects/T1000.py:
add configuration for memory mapped disk
src/dev/sparc/SConscript:
add memory mapped disk to sconscript
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extra : convert_revision : d8df4a455cf48000042d0ff93a274985f4dbe905
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tell if the script is run from m5 as the m5 script
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extra : convert_revision : 06f646cbb8c82444ef345115aa49324a4d3a2c9f
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formats for time (strings, datetime objects, etc.)
Advance system time to 1/1/2009
Clean up time management code a little bit
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extra : convert_revision : 28ebecc7ea6b12f4345c77a9a6b4bdf2e752c4f8
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into iceaxe.:/Volumes/work/m5/incoming
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extra : convert_revision : dad5311afaaf40c1378017514c8b3f73852f13f5
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--HG--
extra : convert_revision : f5a940a8b9aaba0703781b398cf29be581907c21
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : afd4266bd494bb8f127c06985f343219ded4f637
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Make our replacement algorithm same as legion (although not same as the spec)
itb should be 64 entries not 48
src/arch/sparc/tlb.cc:
Bug fixes in the TLB
Make our replacement algorithm same as legion (although not same as the spec)
src/arch/sparc/tlb.hh:
Make our replacement algorithm same as legion (although not same as the spec)
src/python/m5/objects/SparcTLB.py:
itb should be 64 entries too
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extra : convert_revision : 1b5cb3597091e3cfe293e94f6f2219b1e621c35f
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extra : convert_revision : 8ad7824885a5c4da80175c47ba5288aab55b06ca
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m5.internal.event.create(). It takes a python object and a
Tick and calls process() when the Tick occurs.
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extra : convert_revision : 5e4c9728982b206163ff51e6850a1497d85ad7a3
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extra : convert_revision : 3aaf540a9e314a88a8945579398f0d79aa85d5cf
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src/python/swig/init.cc so that it's not as easy to forget
about it when you add a new swig module.
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extra : convert_revision : 5cc4ec0838e636aa761901effb8986de58d23e03
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--HG--
extra : convert_revision : c8309a8774265a707c87c4f516bec1f81aff4a79
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into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
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extra : convert_revision : 6e58629b1e51f1fc493a89f16c3f2e676dc5d191
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src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
add sparc error asi
src/arch/sparc/faults.cc:
put a panic in if TL == MaxTL
src/arch/sparc/isa/decoder.isa:
Hpstate needs to be updated on a done too
src/arch/sparc/miscregfile.cc:
warn istead of panicing of fprs/fsr accesses
src/arch/sparc/tlb.cc:
add sparc error register code that just does nothing
fix a couple of other tlb bugs
src/arch/sparc/ua2005.cc:
fix implementation of HPSTATE write
src/cpu/exetrace.cc:
let exectrate mess up a couple of times before dying
src/python/m5/objects/T1000.py:
add l2 error status register fake devices
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extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca
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configs/common/FSConfig.py:
seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config.
src/arch/sparc/isa/decoder.isa:
change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect
src/arch/sparc/miscregfile.cc:
For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this).
Use instruction count from cpu rather than cycles because that is what legion does
we can change it back after were done with legion
src/base/bitfield.hh:
add a new function mbits() that just masks off bits of interest but doesn't shift
src/cpu/base.cc:
src/cpu/base.hh:
add instruction count to cpu
src/cpu/exetrace.cc:
src/cpu/m5legion_interface.h:
compare instruction count between legion and m5 too
src/cpu/simple/atomic.cc:
change asserts of packet success to if panics wrapped with NDEBUG defines
so we can get some more useful information when we have a bad address
src/dev/isa_fake.cc:
src/dev/isa_fake.hh:
src/python/m5/objects/Device.py:
expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses
src/python/m5/objects/System.py:
convert some tabs to spaces
src/python/m5/objects/T1000.py:
add more fake devices for each l1 bank and each memory controller
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extra : convert_revision : 520814e193b9e86b6410f3ab98d62ed131d295aa
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get symbols for where it's copied to in memory
Add the ability to use an address mask for symbol loading
Rather then silently failing on platform accesses panic
Move BadAddr/IsaFake no Device from Tsunami
Let the system kernel be none, but warn about it
configs/common/FSConfig.py:
We don't have a kernel for sparc yet
src/arch/sparc/system.cc:
Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory
src/base/loader/aout_object.cc:
src/base/loader/aout_object.hh:
src/base/loader/ecoff_object.cc:
src/base/loader/ecoff_object.hh:
src/base/loader/elf_object.cc:
src/base/loader/elf_object.hh:
src/base/loader/object_file.hh:
src/base/loader/raw_object.cc:
src/base/loader/raw_object.hh:
Add the ability to use an address mask for symbol loading
src/dev/sparc/t1000.cc:
Rather then silently failing on platform accesses panic
src/dev/sparc/t1000.hh:
fix up a couple of platform comments
src/python/m5/objects/Bus.py:
src/python/m5/objects/Device.py:
src/python/m5/objects/T1000.py:
src/python/m5/objects/Tsunami.py:
Move BadAddr/IsaFake no Device from Tsunami
src/python/m5/objects/System.py:
Let kernel be none
src/sim/system.cc:
Let the system kernel be none, but warn about it
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extra : convert_revision : 92f6afef599a3d3c7c5026d03434102c41c7b5f4
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we can make our own hypervisor binary, we probably won't need it.
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extra : convert_revision : 168883e4a5d3760962cd9759a6f41c66f5a6402a
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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extra : convert_revision : 75f3398e38e18eb1f8248e23708d7a8d8cce0fc5
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description.
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extra : convert_revision : a2d3cf29ab65c61af27d82a8c421a41a19fd5aeb
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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extra : convert_revision : 74b2352b8f088e38cd1ecf3a8233b45df0476d93
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into zower.eecs.umich.edu:/home/gblack/m5/newmemmemops
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extra : convert_revision : c49b760eac758dbde30867cb638fcb3b790f4721
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configs/common/FSConfig.py:
Make a SPARC system create an IO bus.
src/python/m5/objects/T1000.py:
Create a T1000 platform
src/arch/sparc/miscregfile.cc:
Initialize the strand status register to the value legion provides.
src/cpu/exetrace.cc:
Truncate an ExtMachInst to a MachInst before comparing with Legion.
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extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
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extra : convert_revision : 966246877ac1f1e6c2675d413b0b405cccfecbeb
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