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AgeCommit message (Expand)Author
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2017-01-03python: Don't use Swig to cast statsAndreas Sandberg
2017-01-03sim: Remove redundant export_method_cxx_predeclsAndreas Sandberg
2016-12-19python: Export periodicStatDumpAndreas Sandberg
2016-09-15base: eliminate ipython warningCurtis Dunham
2016-09-13misc: Remove FullSystem check for networking componentsMichael LeBeane
2016-09-13base: Output all AddrRange parameters to config.iniMatt Poremba
2016-05-27power: Allow voltage to be configured via cmd lineAkash Bagdia
2016-04-06misc: Bail out of DVFS dot if we cannot resolve the domainsSascha Bischoff
2015-12-15misc: Add secondary dot output for DVFS domainsSascha Bischoff
2016-03-30misc: Don't build region.py as a PySourceAndreas Sandberg
2016-03-30style: Refactor the style checker as a Python packageAndreas Sandberg
2015-11-26sim: Add support for forkingAndreas Sandberg
2015-11-26sim: Add support for notifying Drainable objects of a forkAndreas Sandberg
2015-11-27base: Add support for changing output directoriesAndreas Sandberg
2016-02-13configs: add command-line option to stop debug outputMichael LeBeane
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
2016-02-06style: remove trailing whitespaceSteve Reinhardt
2016-01-17sim: fix redundant --debug-start help stringSteve Reinhardt
2016-01-17sim: don't ignore SIG_TRAPSteve Reinhardt
2015-12-10dev: Move network devices to src/dev/net/Andreas Sandberg
2015-12-01config: Fix broken SimObject listingAndreas Sandberg
2015-11-22config: Added missing types to JSON/INI Python readerAndrew Bardsley
2015-10-06sim: print pid in output headerSteve Reinhardt
2015-09-30base: remove Trace::enabled flagCurtis Dunham
2015-08-14ruby: Expose MessageBuffers as SimObjectsJoel Hestness
2015-07-07sim: Decouple draining from the SimObject hierarchyAndreas Sandberg
2015-07-07sim: Move mem(Writeback|Invalidate) to SimObjectAndreas Sandberg
2015-07-07python: Remove redundant drain when changing memory modesAndreas Sandberg
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-03-23misc: quote args in echoed command lineSteve Reinhardt
2015-02-03base: Add XOR-based hashed address interleavingAndreas Hansson
2015-02-03config: Fix typo in Float paramGeoffrey Blake
2014-12-23sim: fix reference counting of PythonEventCurtis Dunham
2014-12-02scons: Ensure dictionary iteration is sorted by keyAndreas Hansson
2014-11-12sim: Sort SimObject descendants and portsAndreas Hansson
2014-11-06ruby: interface with classic memory controllerNilay Vaish
2014-10-16sim: EventQueue wakeup on events scheduled outside the event loopAndreas Hansson
2014-10-16base: Reimplement the DPRINTF mechanism in a Logger classAndrew Bardsley
2014-10-16config: Add the ability to read a config file using C++ and PythonAndreas Hansson
2014-10-16config: Add a --without-python option to build processAndrew Bardsley
2014-10-11sim: draining bug for fast-forwaring multiple coresAndrew Lukefahr
2014-10-09config: Add Current as a parameter typeAndreas Hansson
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-09-20config: Cleanup .json config file generationAndrew Bardsley
2014-09-09config: Fix vectorparam command line parsingGeoffrey Blake
2014-09-03config: Add port splicing capability to PortRef classGeoffrey Blake
2014-09-03config: Change parsing of Addr so hex values work from scriptsMitch Hayenga
2014-09-01ruby: message buffers: significant changesNilay Vaish
2014-08-10config: Add hooks to enable new config sysGeoffrey Blake
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