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AgeCommit message (Expand)Author
2006-11-13Expose debugBreakCycle through swig and get rid ofNathan Binkert
2006-11-12Create a module called internal where swigged stuff goes.Nathan Binkert
2006-11-11Fix TypoNathan Binkert
2006-11-11Get rid of the ParamContext for pseudo instructions and moveNathan Binkert
2006-11-09Get SPARC to the point that it starts running. Add ability to load the ROM bi...Ali Saidi
2006-11-08simplify maxtick parsing in both the python and the c++.Lisa Hsu
2006-11-08Remove mem parameter. Should have been removed earlier.Kevin Lim
2006-11-08Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-11-07add code to operate in lockstep with legionAli Saidi
2006-11-07Fix error message.Kevin Lim
2006-11-07Remove hack by setting configuration better.Kevin Lim
2006-11-06delete pcifake, tsunamifake. Combine BadAddr/IsaFake into oneAli Saidi
2006-11-02Have bus use the BadAddress device to handle bad addresses. The O3 CPU shoul...Kevin Lim
2006-10-24Merge zizzer:/bk/newmemAli Saidi
2006-10-23Merge zizzer:/bk/newmemLisa Hsu
2006-10-23get rid of the "resume" step at the end of changeToTiming/Atomic because this...Lisa Hsu
2006-10-20Use fixPacket function everywhere.Ron Dreslinski
2006-10-20Merge zizzer:/bk/newmemAli Saidi
2006-10-20still working on getting past initializationAli Saidi
2006-10-18how did i not commit this already? the other way doesn't seem to work, need ...Lisa Hsu
2006-10-18Get rid of obsolete in-cache copy support.Steve Reinhardt
2006-10-17Enable MP systems via cmd-line flag in fs.py.Steve Reinhardt
2006-10-12Merge zizzer:/bk/newmemLisa Hsu
2006-10-11System not global object, need to preface it with objects.Lisa Hsu
2006-10-11since memoryMode was put into the System (from SimObject), things got broken ...Lisa Hsu
2006-10-11More cache fixes. Atomic coherence now works as well.Ron Dreslinski
2006-10-09Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-10-09Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-10-09Make memtest work with 8 memtestersRon Dreslinski
2006-10-09Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
2006-10-09Update the Memtester, commit a config file/test for it.Ron Dreslinski
2006-10-08Fixes for Port proxies and proxy parameters.Steve Reinhardt
2006-10-08Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-10-08bus changesGabe Black
2006-10-08Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)Steve Reinhardt
2006-10-08Clean up configs.Kevin Lim
2006-10-05Partial reimplementation of the bus. The "clock" and "width" parameters have ...Gabe Black
2006-10-02Oops, forgot to assign the option to the param context.Kevin Lim
2006-10-02Add in ability to start a trace at a specific cycle.Kevin Lim
2006-10-02Updates to fix merge issues and bring almost everything up to working speed. ...Kevin Lim
2006-09-30Merge ktlim@zamp:./local/clean/o3-merge/m5Kevin Lim
2006-09-18add boiler plate intel nic codeAli Saidi
2006-09-15Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-09-08Add support for assigning lists of ports or proxies to VectorPorts.Steve Reinhardt
2006-09-06Try to make unproxy order more deterministic.Steve Reinhardt
2006-09-05Enable proxies (Self/Parent) for specifying ports.Steve Reinhardt
2006-09-05Print ports in config.ini as well.Steve Reinhardt
2006-09-04More Python hacking to deal with config.py splitSteve Reinhardt
2006-09-04Split config.py into multiple files.Steve Reinhardt
2006-09-04config.py:Steve Reinhardt
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