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2007-02-21Get rid of the ConsoleListener SimObject and just fold theNathan Binkert
relevant code directly into the SimConsole object. Now, you can easily turn off the listen port by just specifying 0 as the port. --HG-- extra : convert_revision : c8937fa45b429d8a0728e6c720a599e38972aaf0
2007-02-21Fix tracing so it starts right away if --trace-start is notNathan Binkert
specified. --HG-- extra : convert_revision : 49c1ea0b8c313949124aed84b1055db0b3c55bd8
2007-02-21Automatically generate m5/internal/__init__.py and swig/init.ccNathan Binkert
based on the swig modules that we have --HG-- extra : convert_revision : 2fd12db39d46608a62b9df36c2b36189f1d2bc30
2007-02-18Get rid of the stand alone ParamContext since all of theNathan Binkert
relevant stuff has now been moved to python. --HG-- extra : convert_revision : 608e5ffd0e2b33949a2b183117216f136cfa4484
2007-02-18Get rid of the Serialize and IntervalStats Param contextsNathan Binkert
since they're no longer used --HG-- extra : convert_revision : e39590aa03cc4c961d2eb5dab57862811f431e4d
2007-02-17Get rid of the Statistics and Statreset ParamContexts, andNathan Binkert
expose all of the relevant functionality to python. Clean up the mysql code while we're at it. --HG-- extra : convert_revision : 5b711202a5a452b8875ebefb136a156b65c24279
2007-02-17Default to tracing being disabled in C++, it will be turnedNathan Binkert
on in python. Fix the trace start code so it actually starts when it is suppsed to. Make the Exec tracing stuff obey the trace enabled flag. --HG-- extra : convert_revision : 634ba0b4f52345d4bf40d43e239cef7ef43e7691
2007-02-17Pass an exception from a python event through the event queueNathan Binkert
back into python so we don't just silently ignore those errors --HG-- extra : convert_revision : e2f5566a4681f1b8ea80af50071119118afa7d8a
2007-02-13Make mulitple consoles work and be distinguishable from each otherAli Saidi
src/dev/alpha/tsunamireg.h: get rid of things that aren't really tsunami registers src/dev/platform.hh: src/dev/uart.cc: the uart pointer isn't used anymore src/dev/simconsole.cc: make the simconsole print something more useful to distinguish between various consoles in a single system src/dev/uart8250.hh: put the needed uart defines in here rather than including them from tsunamireg src/python/m5/objects/T1000.py: add a console to the T1000 config for the hypervisor --HG-- extra : convert_revision : 76ca92122e611eaf76b989bc699582eef8297be8
2007-02-13Merge all of the execution trace configuration stuff intoNathan Binkert
the traceflags infrastructure. InstExec is now just Exec and all of the command line options are now trace options. --HG-- extra : convert_revision : 4adfa9dfbb32622d30ef4e63c06c7d87da793c8f
2007-02-13Rearrange traceflags.py so that the file generation only happens ifNathan Binkert
the script is invoked as main. This allows us to import traceflags.py if we just want the list of available flags. Embed traceflags.py into the zipfile so it can be accessed from the python side of things. With this, print an error on invalid flags and add --trace-help option that will print out the list of trace flags that are compiled in. If a flag is prefixed with a '-', now that flag will be disabled. --HG-- extra : convert_revision : 2260a596b07d127c582ff73474dbbdb0583db524
2007-02-10Clean up tracing stuff more, get rid of the trace log sinceNathan Binkert
its not all that useful. Fix a few bugs with python/C++ integration. --HG-- extra : convert_revision : a706512f7dc8b0c88f1ff96fe35ab8fbf9548b78
2007-02-09Get rid of the Random context and add the support directly to python.Nathan Binkert
We don't currently use randomness much, so I didn't go too far, but in the future, we may want to actually expose the random number values themselves to python. For now, I'll at least let you seed it. While we're at it, clean up a clearly bad way for generating random doubles. --HG-- extra : convert_revision : df2aa8b58dd0d9c2a7c771668a760b2df8db1e11
2007-02-09Clean up from my last commit to the trace stuff.Nathan Binkert
--HG-- extra : convert_revision : b6a975d1c4195a764ba875bc3aaaa064be4955b7
2007-02-09Get rid of the Trace ParamContext and give python directNathan Binkert
access to enabling/disabling tracing. Command line is unchanged except for the removal of --trace-cycle since it's not so clear what that means. --HG-- extra : convert_revision : c0164d92d3615d76d0c6acaabaafd92a9278212a
2007-01-31make sparc fs less chattyAli Saidi
src/SConscript: strip doesn't take a src and dest in solaris --HG-- extra : convert_revision : 57f95eda0e3232475a5b55753ace3f3f0fced8b3
2007-01-25Move time forward to Jan 1, 2009 and update statsNathan Binkert
--HG-- extra : convert_revision : 9398362237443dc659f423a342bd27c923e90aea
2007-01-25Instead of passing an int to represent time between python and C++Nathan Binkert
pass the tuple of python's struct_time and interpret that. Fixes a problem where the local timezone leaked into the time calculation. Also fix things so that the unix, python, and RTC data sheets all get the right time. Provide both years since 1900 and BCD two digit year. Put the date back at 1/1/2006 for now. --HG-- extra : convert_revision : 473244572f468de2cb579a3dd7ae296a6f81f5d7
2007-01-21add dumb time of day deviceAli Saidi
--HG-- extra : convert_revision : 52e51ff49f7ed73065f04707ded06dc7254292c4
2007-01-09add memory mapped disk deviceAli Saidi
configs/common/FSConfig.py: src/python/m5/objects/T1000.py: add configuration for memory mapped disk src/dev/sparc/SConscript: add memory mapped disk to sconscript --HG-- extra : convert_revision : d8df4a455cf48000042d0ff93a274985f4dbe905
2007-01-03set __name__ in the root m5 script to __m5_main__ so we canNathan Binkert
tell if the script is run from m5 as the m5 script --HG-- extra : convert_revision : 06f646cbb8c82444ef345115aa49324a4d3a2c9f
2007-01-03Add 'Time' as a parameter type that can accept variousNathan Binkert
formats for time (strings, datetime objects, etc.) Advance system time to 1/1/2009 Clean up time management code a little bit --HG-- extra : convert_revision : 28ebecc7ea6b12f4345c77a9a6b4bdf2e752c4f8
2006-12-29Merge zizzer.eecs.umich.edu:/bk/newmemNathan Binkert
into iceaxe.:/Volumes/work/m5/incoming --HG-- extra : convert_revision : dad5311afaaf40c1378017514c8b3f73852f13f5
2006-12-29FormattingNathan Binkert
--HG-- extra : convert_revision : f5a940a8b9aaba0703781b398cf29be581907c21
2006-12-27Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : afd4266bd494bb8f127c06985f343219ded4f637
2006-12-27Bug fixes in the TLBAli Saidi
Make our replacement algorithm same as legion (although not same as the spec) itb should be 64 entries not 48 src/arch/sparc/tlb.cc: Bug fixes in the TLB Make our replacement algorithm same as legion (although not same as the spec) src/arch/sparc/tlb.hh: Make our replacement algorithm same as legion (although not same as the spec) src/python/m5/objects/SparcTLB.py: itb should be 64 entries too --HG-- extra : convert_revision : 1b5cb3597091e3cfe293e94f6f2219b1e621c35f
2006-12-21Fix copyrightNathan Binkert
--HG-- extra : convert_revision : 8ad7824885a5c4da80175c47ba5288aab55b06ca
2006-12-21Expose the C++ event queue to python via the python functionNathan Binkert
m5.internal.event.create(). It takes a python object and a Tick and calls process() when the Tick occurs. --HG-- extra : convert_revision : 5e4c9728982b206163ff51e6850a1497d85ad7a3
2006-12-21Create a wrapper function to more easily add swig stuff to the buildNathan Binkert
--HG-- extra : convert_revision : 3aaf540a9e314a88a8945579398f0d79aa85d5cf
2006-12-21move the swig initialization calls from src/sim/main.cc toNathan Binkert
src/python/swig/init.cc so that it's not as easy to forget about it when you add a new swig module. --HG-- extra : convert_revision : 5cc4ec0838e636aa761901effb8986de58d23e03
2006-12-15small change to eliminate address range overlap.Lisa Hsu
--HG-- extra : convert_revision : c8309a8774265a707c87c4f516bec1f81aff4a79
2006-12-12Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 --HG-- extra : convert_revision : 6e58629b1e51f1fc493a89f16c3f2e676dc5d191
2006-12-07get legion/m5 to first tlb miss faultAli Saidi
src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: add sparc error asi src/arch/sparc/faults.cc: put a panic in if TL == MaxTL src/arch/sparc/isa/decoder.isa: Hpstate needs to be updated on a done too src/arch/sparc/miscregfile.cc: warn istead of panicing of fprs/fsr accesses src/arch/sparc/tlb.cc: add sparc error register code that just does nothing fix a couple of other tlb bugs src/arch/sparc/ua2005.cc: fix implementation of HPSTATE write src/cpu/exetrace.cc: let exectrate mess up a couple of times before dying src/python/m5/objects/T1000.py: add l2 error status register fake devices --HG-- extra : convert_revision : ed5dfdfb28633bf36e5ae07d244f7510a02874ca
2006-12-04More changes to get SPARC fs closer. Now at 1.2M cycles before differenceAli Saidi
configs/common/FSConfig.py: seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config. src/arch/sparc/isa/decoder.isa: change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect src/arch/sparc/miscregfile.cc: For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this). Use instruction count from cpu rather than cycles because that is what legion does we can change it back after were done with legion src/base/bitfield.hh: add a new function mbits() that just masks off bits of interest but doesn't shift src/cpu/base.cc: src/cpu/base.hh: add instruction count to cpu src/cpu/exetrace.cc: src/cpu/m5legion_interface.h: compare instruction count between legion and m5 too src/cpu/simple/atomic.cc: change asserts of packet success to if panics wrapped with NDEBUG defines so we can get some more useful information when we have a bad address src/dev/isa_fake.cc: src/dev/isa_fake.hh: src/python/m5/objects/Device.py: expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses src/python/m5/objects/System.py: convert some tabs to spaces src/python/m5/objects/T1000.py: add more fake devices for each l1 bank and each memory controller --HG-- extra : convert_revision : 8024ae07b765a04ff6f600e5875b55d8a7d3d276
2006-12-02Support better param conversions to/from numeric subclasses.Steve Reinhardt
--HG-- extra : convert_revision : 2ccb75b0912a384789458710fd9bbb65626f839e
2006-12-02Fix help strings on GenRepl params.Steve Reinhardt
--HG-- extra : convert_revision : 520814e193b9e86b6410f3ab98d62ed131d295aa
2006-11-30Load the hypervisor symbols twice, once with an address mask so that we can ↵Ali Saidi
get symbols for where it's copied to in memory Add the ability to use an address mask for symbol loading Rather then silently failing on platform accesses panic Move BadAddr/IsaFake no Device from Tsunami Let the system kernel be none, but warn about it configs/common/FSConfig.py: We don't have a kernel for sparc yet src/arch/sparc/system.cc: Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory src/base/loader/aout_object.cc: src/base/loader/aout_object.hh: src/base/loader/ecoff_object.cc: src/base/loader/ecoff_object.hh: src/base/loader/elf_object.cc: src/base/loader/elf_object.hh: src/base/loader/object_file.hh: src/base/loader/raw_object.cc: src/base/loader/raw_object.hh: Add the ability to use an address mask for symbol loading src/dev/sparc/t1000.cc: Rather then silently failing on platform accesses panic src/dev/sparc/t1000.hh: fix up a couple of platform comments src/python/m5/objects/Bus.py: src/python/m5/objects/Device.py: src/python/m5/objects/T1000.py: src/python/m5/objects/Tsunami.py: Move BadAddr/IsaFake no Device from Tsunami src/python/m5/objects/System.py: Let kernel be none src/sim/system.cc: Let the system kernel be none, but warn about it --HG-- extra : convert_revision : 92f6afef599a3d3c7c5026d03434102c41c7b5f4
2006-11-22Added a parameter to set memory to zero. This is to support Legion, and once ↵Gabe Black
we can make our own hypervisor binary, we probably won't need it. --HG-- extra : convert_revision : 168883e4a5d3760962cd9759a6f41c66f5a6402a
2006-11-22Merge zizzer:/bk/sparcfsGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 75f3398e38e18eb1f8248e23708d7a8d8cce0fc5
2006-11-20Add in rom/rams for the nvram, hypervisor description, and partition ↵Gabe Black
description. --HG-- extra : convert_revision : a49de5fcfbea307c971964b8a68b95eb5d9a2bf4
2006-11-16Implement current working directory for LiveProcessesNathan Binkert
--HG-- extra : convert_revision : a2d3cf29ab65c61af27d82a8c421a41a19fd5aeb
2006-11-16Merge zower.eecs.umich.edu:/home/gblack/m5/newmemmemopsGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 74b2352b8f088e38cd1ecf3a8233b45df0476d93
2006-11-16Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
into zower.eecs.umich.edu:/home/gblack/m5/newmemmemops --HG-- extra : convert_revision : c49b760eac758dbde30867cb638fcb3b790f4721
2006-11-16Fixes for SPARC_FSGabe Black
configs/common/FSConfig.py: Make a SPARC system create an IO bus. src/python/m5/objects/T1000.py: Create a T1000 platform src/arch/sparc/miscregfile.cc: Initialize the strand status register to the value legion provides. src/cpu/exetrace.cc: Truncate an ExtMachInst to a MachInst before comparing with Legion. --HG-- extra : convert_revision : e4189b572a5297e8362f5bd26d87b74736c8e5f1
2006-11-14Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops --HG-- extra : convert_revision : 966246877ac1f1e6c2675d413b0b405cccfecbeb
2006-11-14Merge 141.212.106.238:/home/gblack/m5/newmemmemopsGabe Black
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem --HG-- extra : convert_revision : 8e805b9bbd5c64c2e5951384b3c6ef712062d08c
2006-11-14Create a stub t1000 platform.Gabe Black
--HG-- extra : convert_revision : 7e27b23b66c743b4625a1dd9d8d6ba61bff45168
2006-11-14Update phase param in the .py file for the cpusRon Dreslinski
--HG-- extra : convert_revision : cd2eb8c00adcb34b8693a4d1a66187927c0f6803
2006-11-13Expose debugBreakCycle through swig and get rid ofNathan Binkert
the Debug param context --HG-- extra : convert_revision : 40e9dcfa9faedbe0c90a43f908f20a7c14ded6a4
2006-11-12Create a module called internal where swigged stuff goes.Nathan Binkert
Rename cc_main to internal.main --HG-- extra : convert_revision : e938005f600fbf8a43435e29426a948f4501f072
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 21:41:24 +0000