index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
python
Age
Commit message (
Expand
)
Author
2006-11-22
Added a parameter to set memory to zero. This is to support Legion, and once ...
Gabe Black
2006-11-22
Merge zizzer:/bk/sparcfs
Gabe Black
2006-11-20
Add in rom/rams for the nvram, hypervisor description, and partition descript...
Gabe Black
2006-11-16
Implement current working directory for LiveProcesses
Nathan Binkert
2006-11-16
Merge zower.eecs.umich.edu:/home/gblack/m5/newmemmemops
Gabe Black
2006-11-16
Merge zizzer.eecs.umich.edu:/bk/newmem/
Gabe Black
2006-11-16
Fixes for SPARC_FS
Gabe Black
2006-11-14
Merge zizzer.eecs.umich.edu:/bk/newmem/
Gabe Black
2006-11-14
Merge 141.212.106.238:/home/gblack/m5/newmemmemops
Gabe Black
2006-11-14
Create a stub t1000 platform.
Gabe Black
2006-11-14
Update phase param in the .py file for the cpus
Ron Dreslinski
2006-11-13
Expose debugBreakCycle through swig and get rid of
Nathan Binkert
2006-11-12
Create a module called internal where swigged stuff goes.
Nathan Binkert
2006-11-11
Fix Typo
Nathan Binkert
2006-11-11
Get rid of the ParamContext for pseudo instructions and move
Nathan Binkert
2006-11-09
Get SPARC to the point that it starts running. Add ability to load the ROM bi...
Ali Saidi
2006-11-08
simplify maxtick parsing in both the python and the c++.
Lisa Hsu
2006-11-08
Remove mem parameter. Should have been removed earlier.
Kevin Lim
2006-11-08
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2006-11-07
add code to operate in lockstep with legion
Ali Saidi
2006-11-07
Fix error message.
Kevin Lim
2006-11-07
Remove hack by setting configuration better.
Kevin Lim
2006-11-06
delete pcifake, tsunamifake. Combine BadAddr/IsaFake into one
Ali Saidi
2006-11-02
Have bus use the BadAddress device to handle bad addresses. The O3 CPU shoul...
Kevin Lim
2006-10-24
Merge zizzer:/bk/newmem
Ali Saidi
2006-10-23
Merge zizzer:/bk/newmem
Lisa Hsu
2006-10-23
get rid of the "resume" step at the end of changeToTiming/Atomic because this...
Lisa Hsu
2006-10-20
Use fixPacket function everywhere.
Ron Dreslinski
2006-10-20
Merge zizzer:/bk/newmem
Ali Saidi
2006-10-20
still working on getting past initialization
Ali Saidi
2006-10-18
how did i not commit this already? the other way doesn't seem to work, need ...
Lisa Hsu
2006-10-18
Get rid of obsolete in-cache copy support.
Steve Reinhardt
2006-10-17
Enable MP systems via cmd-line flag in fs.py.
Steve Reinhardt
2006-10-12
Merge zizzer:/bk/newmem
Lisa Hsu
2006-10-11
System not global object, need to preface it with objects.
Lisa Hsu
2006-10-11
since memoryMode was put into the System (from SimObject), things got broken ...
Lisa Hsu
2006-10-11
More cache fixes. Atomic coherence now works as well.
Ron Dreslinski
2006-10-09
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2006-10-09
Merge zizzer.eecs.umich.edu:/bk/newmem
Gabe Black
2006-10-09
Make memtest work with 8 memtesters
Ron Dreslinski
2006-10-09
Merge zizzer:/z/m5/Bitkeeper/newmem
Ron Dreslinski
2006-10-09
Update the Memtester, commit a config file/test for it.
Ron Dreslinski
2006-10-08
Fixes for Port proxies and proxy parameters.
Steve Reinhardt
2006-10-08
Merge zizzer.eecs.umich.edu:/bk/newmem
Gabe Black
2006-10-08
bus changes
Gabe Black
2006-10-08
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
Steve Reinhardt
2006-10-08
Clean up configs.
Kevin Lim
2006-10-05
Partial reimplementation of the bus. The "clock" and "width" parameters have ...
Gabe Black
2006-10-02
Oops, forgot to assign the option to the param context.
Kevin Lim
2006-10-02
Add in ability to start a trace at a specific cycle.
Kevin Lim
[next]