summaryrefslogtreecommitdiff
path: root/src/sim/SConscript
AgeCommit message (Expand)Author
2015-02-11sim: Move the BaseTLB to src/arch/generic/Andreas Sandberg
2014-10-16config: Add the ability to read a config file using C++ and PythonAndreas Hansson
2014-10-16config: Add a --without-python option to build processAndrew Bardsley
2014-08-10config: Add SubSystem container for simobjectsGeoffrey Blake
2014-07-23cpu: `Minor' in-order CPU modelAndrew Bardsley
2014-06-30power: Add basic DVFS support for gem5Stephan Diestelhorst
2013-11-25sim: simulate with multiple threads and event queuesSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-06-03sim: Add debug output when executing pseudo-instructionsAndreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-08-21Clock: Move the clock and related functions to ClockedObjectAndreas Hansson
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...Anthony Gutierrez
2011-11-02SE/FS: Get rid of FULL_SYSTEM in sim.Gabe Black
2011-10-30SE/FS: Compile in system events in SE mode.Gabe Black
2011-10-30SE/FS: Build syscall_emul.cc in FS mode.Gabe Black
2011-10-30SE/FS: Build the base process class in FS.Gabe Black
2011-06-02scons: rename TraceFlags to DebugFlagsNathan Binkert
2011-04-15scons: make a flexible system for guarding source filesNathan Binkert
2011-02-06m5: added work completed monitoring supportBrad Beckmann
2011-01-19Time: Add a mechanism to prevent M5 from running faster than real time.Gabe Black
2010-11-19SCons: Support building without an ISAAli Saidi
2010-11-08ARM: Add checkpointing supportAli Saidi
2010-07-05sim: fold StartupCallback into SimObjectSteve Reinhardt
2009-05-04scons: re-work the *Source functions to take more information.Nathan Binkert
2009-01-19python: Rework how things are importedNathan Binkert
2008-12-17Make Alpha pseudo-insts available from SE mode.Steve Reinhardt
2008-10-10TLB: Make all tlbs derive from a common base class in both python and C++.Gabe Black
2008-08-03libm5: Create a libm5 static library for embedding m5.Nathan Binkert
2008-06-15add compile flags to m5Nathan Binkert
2007-10-31Traceflags: Add SCons function to created a traceflag instead of having one f...Ali Saidi
2007-08-27Address Translation: Make the Generic TLB only compile in SE mode.Gabe Black
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
2007-08-01Arguments: Get rid of duplicate code for the Arguments class in each architec...Ali Saidi
2007-07-28Turn the instruction tracing code into pluggable sim objects.Gabe Black
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
2007-03-10Rework the way SCons recurses into subdirectories, making itNathan Binkert