gem5 - gem5

Age	Commit message (Expand)	Author
2017-11-27	scons: Switch from "guards" to "tags" on source files.	Gabe Black
2017-03-09	syscall-emul: Adds SE mode signal feature	Brandon Potter
2016-11-09	syscall_emul: [patch 10/22] refactor fdentry and add fdarray class	Brandon Potter
2016-11-09	syscall_emul: [patch 8/22] refactor process class	Brandon Potter
2016-11-09	style: [patch 3/22] reduce include dependencies in some headers	Brandon Potter
2016-11-09	syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc	Brandon Potter
2016-06-06	sim: Adding support for power models	David Guillen Fandos
2016-06-06	pwr: Add power states to ClockedObject	David Guillen Fandos
2016-04-07	Revert to 74c1e6513bd0 (sim: Thermal support for Linux)	Andreas Sandberg
2016-04-06	Revert power patch sets with unexpected interactions	Andreas Sandberg
2016-04-05	power: Add support for power models	David Guillen Fandos
2014-11-18	power: Add power states to ClockedObject	Akash Bagdia
2015-05-12	sim: Adding thermal model support	David Guillen Fandos
2016-03-17	syscall_emul: add extra debug support for syscalls	Alexandru Dutu
2015-12-04	sim: Add support for generating back traces on errors	Andreas Sandberg
2015-09-02	sim: tag-based checkpoint versioning	Curtis Dunham
2015-07-24	base: refactor process class (specifically FdMap and friends)	Brandon Potter
2015-02-11	sim: Move the BaseTLB to src/arch/generic/	Andreas Sandberg
2014-10-16	config: Add the ability to read a config file using C++ and Python	Andreas Hansson
2014-10-16	config: Add a --without-python option to build process	Andrew Bardsley
2014-08-10	config: Add SubSystem container for simobjects	Geoffrey Blake
2014-07-23	cpu: `Minor' in-order CPU model	Andrew Bardsley
2014-06-30	power: Add basic DVFS support for gem5	Stephan Diestelhorst
2013-11-25	sim: simulate with multiple threads and event queues	Steve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2013-09-04	arch: Resurrect the NOISA build target and rename it NULL	Andreas Hansson
2013-08-19	power: Add voltage domains to the clock domains	Akash Bagdia
2013-06-27	sim: Add the notion of clock domains to all ClockedObjects	Akash Bagdia
2013-06-03	sim: Add debug output when executing pseudo-instructions	Andreas Sandberg
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-08-21	Clock: Move the clock and related functions to ClockedObject	Andreas Hansson
2012-08-15	O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...	Anthony Gutierrez
2011-11-02	SE/FS: Get rid of FULL_SYSTEM in sim.	Gabe Black
2011-10-30	SE/FS: Compile in system events in SE mode.	Gabe Black
2011-10-30	SE/FS: Build syscall_emul.cc in FS mode.	Gabe Black
2011-10-30	SE/FS: Build the base process class in FS.	Gabe Black
2011-06-02	scons: rename TraceFlags to DebugFlags	Nathan Binkert
2011-04-15	scons: make a flexible system for guarding source files	Nathan Binkert
2011-02-06	m5: added work completed monitoring support	Brad Beckmann
2011-01-19	Time: Add a mechanism to prevent M5 from running faster than real time.	Gabe Black
2010-11-19	SCons: Support building without an ISA	Ali Saidi
2010-11-08	ARM: Add checkpointing support	Ali Saidi
2010-07-05	sim: fold StartupCallback into SimObject	Steve Reinhardt
2009-05-04	scons: re-work the *Source functions to take more information.	Nathan Binkert
2009-01-19	python: Rework how things are imported	Nathan Binkert
2008-12-17	Make Alpha pseudo-insts available from SE mode.	Steve Reinhardt
2008-10-10	TLB: Make all tlbs derive from a common base class in both python and C++.	Gabe Black
2008-08-03	libm5: Create a libm5 static library for embedding m5.	Nathan Binkert
2008-06-15	add compile flags to m5	Nathan Binkert
2007-10-31	Traceflags: Add SCons function to created a traceflag instead of having one f...	Ali Saidi
2007-08-27	Address Translation: Make the Generic TLB only compile in SE mode.	Gabe Black