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path: root/src/sim/SConscript
AgeCommit message (Expand)Author
2019-04-28arch, sim: Simplify the AuxVector type.Gabe Black
2019-04-25sim-se: add a faux-filesystemDavid Hashe
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
2019-03-15mem: Move the Port base class into sim.Gabe Black
2017-11-27scons: Switch from "guards" to "tags" on source files.Gabe Black
2017-03-09syscall-emul: Adds SE mode signal featureBrandon Potter
2016-11-09syscall_emul: [patch 10/22] refactor fdentry and add fdarray classBrandon Potter
2016-11-09syscall_emul: [patch 8/22] refactor process classBrandon Potter
2016-11-09style: [patch 3/22] reduce include dependencies in some headersBrandon Potter
2016-11-09syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .ccBrandon Potter
2016-06-06sim: Adding support for power modelsDavid Guillen Fandos
2016-06-06pwr: Add power states to ClockedObjectDavid Guillen Fandos
2016-04-07Revert to 74c1e6513bd0 (sim: Thermal support for Linux)Andreas Sandberg
2016-04-06Revert power patch sets with unexpected interactionsAndreas Sandberg
2016-04-05power: Add support for power modelsDavid Guillen Fandos
2014-11-18power: Add power states to ClockedObjectAkash Bagdia
2015-05-12sim: Adding thermal model supportDavid Guillen Fandos
2016-03-17syscall_emul: add extra debug support for syscallsAlexandru Dutu
2015-12-04sim: Add support for generating back traces on errorsAndreas Sandberg
2015-09-02sim: tag-based checkpoint versioningCurtis Dunham
2015-07-24base: refactor process class (specifically FdMap and friends)Brandon Potter
2015-02-11sim: Move the BaseTLB to src/arch/generic/Andreas Sandberg
2014-10-16config: Add the ability to read a config file using C++ and PythonAndreas Hansson
2014-10-16config: Add a --without-python option to build processAndrew Bardsley
2014-08-10config: Add SubSystem container for simobjectsGeoffrey Blake
2014-07-23cpu: `Minor' in-order CPU modelAndrew Bardsley
2014-06-30power: Add basic DVFS support for gem5Stephan Diestelhorst
2013-11-25sim: simulate with multiple threads and event queuesSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-06-03sim: Add debug output when executing pseudo-instructionsAndreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-08-21Clock: Move the clock and related functions to ClockedObjectAndreas Hansson
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...Anthony Gutierrez
2011-11-02SE/FS: Get rid of FULL_SYSTEM in sim.Gabe Black
2011-10-30SE/FS: Compile in system events in SE mode.Gabe Black
2011-10-30SE/FS: Build syscall_emul.cc in FS mode.Gabe Black
2011-10-30SE/FS: Build the base process class in FS.Gabe Black
2011-06-02scons: rename TraceFlags to DebugFlagsNathan Binkert
2011-04-15scons: make a flexible system for guarding source filesNathan Binkert
2011-02-06m5: added work completed monitoring supportBrad Beckmann
2011-01-19Time: Add a mechanism to prevent M5 from running faster than real time.Gabe Black
2010-11-19SCons: Support building without an ISAAli Saidi
2010-11-08ARM: Add checkpointing supportAli Saidi
2010-07-05sim: fold StartupCallback into SimObjectSteve Reinhardt
2009-05-04scons: re-work the *Source functions to take more information.Nathan Binkert
2009-01-19python: Rework how things are importedNathan Binkert
2008-12-17Make Alpha pseudo-insts available from SE mode.Steve Reinhardt
2008-10-10TLB: Make all tlbs derive from a common base class in both python and C++.Gabe Black
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