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path: root/src/sim/System.py
AgeCommit message (Expand)Author
2020-01-07arch,sim: Promote the m5ops_base param to the System base class.Gabe Black
2019-12-18sim: kernelExtras optional load addressesAdrian Herrera
2019-04-28mem: Minimize the use of MemObject.Gabe Black
2019-04-25sim-se: add a faux-filesystemDavid Hashe
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
2017-11-17sim: Implement load_addr_mask auto-calculationGeoffrey Blake
2017-11-16sim: Add an option to load additional kernel objectsAndreas Sandberg
2017-05-02python: Use PyBind11 instead of SWIG for Python wrappersAndreas Sandberg
2017-02-14sim, kvm: make KvmVM a System parameterCurtis Dunham
2017-02-14sim,kvm,arm: fix typosCurtis Dunham
2017-01-03sim: Remove redundant export_method_cxx_predeclsAndreas Sandberg
2016-12-19sim: Remove redundant buildEnv importAndreas Sandberg
2015-05-12sim: Adding thermal model supportDavid Guillen Fandos
2015-12-18sim: Use the old work item behavior by defaultAndreas Sandberg
2015-12-14sim: Add an option to forward work items to PythonAndreas Sandberg
2015-09-30cpu: Change thread assignments for heterogenous SMTMitch Hayenga
2015-02-16mem: mmap the backing store with MAP_NORESERVEAndreas Hansson
2014-08-13sim: remove kernel mapping check for baremetal workloadsDam Sunwoo
2014-06-30power: Add basic DVFS support for gem5Stephan Diestelhorst
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-06-27config: Add a system clock command-line optionAkash Bagdia
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-01-07config: Do not use hardcoded physmem in fs scriptAndreas Hansson
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-10-25dev: Make default clock more reasonable for system and devicesAndreas Hansson
2012-10-15Clock: Inherit the clock from parent by defaultAndreas Hansson
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-01-28Merge with the main repo.Gabe Black
2012-01-16Merge yet again with the main repository.Gabe Black
2012-01-17MEM: Add the system port as a central access pointAndreas Hansson
2012-01-09sim: Enable sampling of run-time for code-sections marked using pseudo insts.Prakash Ramrakhyani
2012-01-07Merge with main repository.Gabe Black
2011-10-30System: Push boot_cpu_frequency down into the subclasses that actually use it.Gabe Black
2011-10-30SE/FS: Make the system object more consistent between SE and FS.Gabe Black
2011-10-20SimObject: add export_method* hooks to export C++ methods to PythonSteve Reinhardt
2011-10-20scons/swig: refactor some of the scons/SWIG codeSteve Reinhardt
2011-07-10O3: Make sure fetch doesn't go off into the weeds during speculation.Ali Saidi
2011-02-06m5: added work completed monitoring supportBrad Beckmann
2011-02-06mcpat: Adds McPAT performance countersJoel Hestness
2010-09-09scons: use code_formatter wherever we can in the build systemNathan Binkert
2010-08-23Loader: Make the load address mask be a parameter of the system rather than a...Ali Saidi
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
2009-01-29Fix typoNathan Binkert
2007-08-02python: Improve support for python calling back to C++ member functions.Nathan Binkert
2007-06-20Make sure all parameters have default values if they'reNathan Binkert
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
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