gem5 - gem5

Age	Commit message (Expand)	Author
2019-01-30	arch,cpu: Add vector predicate registers	Giacomo Gabrielli
2017-12-13	arm,sparc,x86,base,cpu,sim: Replace the Twin(32\|64)_t types with.	Gabe Black
2016-11-09	style: [patch 3/22] reduce include dependencies in some headers	Brandon Potter
2016-02-06	style: remove trailing whitespace	Steve Reinhardt
2015-07-28	revert 5af8f40d8f2c	Nilay Vaish
2015-07-26	cpu: implements vector registers	Nilay Vaish
2015-01-25	sim: Clean up InstRecord	Ali Saidi
2015-01-25	cpu: Remove all notion that we know when the cpu is misspeculating.	Ali Saidi
2014-11-24	misc: Another round of static analysis fixups	Andreas Hansson
2014-05-09	cpu: Allow setWhen on trace objects	Andrew Bardsley
2011-01-03	Make commenting on close namespace brackets consistent.	Steve Reinhardt
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-08-25	Tracing: Fix trace so 'Predicated False' doesn't show up	Ali Saidi
2010-08-23	CPU: Make Exec trace to print predication result (if false) for memory instru...	Min Kyu Jeong
2009-07-19	Tracing: Add accessors so tracers can get at data in trace records.	Gabe Black
2009-05-17	includes: sort includes again	Nathan Binkert
2009-05-17	types: Move stuff for global types into src/base/types.hh	Nathan Binkert
2009-01-06	Tracing: Make tracing aware of macro and micro ops.	Gabe Black
2008-09-10	style: Remove non-leading tabs everywhere they shouldn't be. Developers shoul...	Ali Saidi
2007-08-30	params: Deprecate old-style constructors; update most SimObject constructors.	Miles Kaufmann
2007-08-01	Twin64_t is in base/bigint.hh	Nathan Binkert
2007-07-28	Turn the instruction tracing code into pluggable sim objects.	Gabe Black