gem5 - gem5

Age	Commit message (Expand)	Author
2015-09-02	sim: tag-based checkpoint versioning	Curtis Dunham
2015-07-07	sim: Refactor the serialization base class	Andreas Sandberg
2013-11-25	sim: simulate with multiple threads and event queues	Steve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2012-11-16	sim: have a curTick per eventq	Nilay Vaish
2012-10-15	Mem: Separate the host and guest views of memory backing store	Andreas Hansson
2012-06-05	sim: Provide a framework for detecting out of data checkpoints and migrating ...	Ali Saidi
2012-03-19	clang: Fix recently introduced clang compilation errors	Andreas Hansson
2012-01-28	SE/FS: Make SE vs. FS mode a runtime parameter.	Gabe Black
2011-06-02	copyright: clean up copyright blocks	Nathan Binkert
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-02-11	Timesync: Make sure timesync event is setup after curTick is unserialized	Ali Saidi
2011-01-19	TimeSync: Use the new setTick and getTick functions.	Gabe Black
2011-01-19	Time: Add a mechanism to prevent M5 from running faster than real time.	Gabe Black
2011-01-10	Root: Get rid of unnecessary includes in root.cc.	Gabe Black
2007-07-23	Major changes to how SimObjects are created and initialized. Almost all	Nathan Binkert
2007-03-06	Move all of the parameters of the Root SimObject so they are	Nathan Binkert
2006-10-06	there are two main thrusts of this changeset.	Lisa Hsu
2006-06-09	Move main control from C++ into Python.	Steve Reinhardt
2006-05-31	Updated Authors from bk prs info	Ali Saidi
2006-05-22	New directory structure:	Steve Reinhardt