gem5 - gem5

Age	Commit message (Expand)	Author
2008-11-05	Right now a single thread cpu 1 could get assigned context Id != 1, depending	Lisa Hsu
2008-11-02	Add in Context IDs to the simulator. From now on, cpuId is almost never used,	Lisa Hsu
2008-11-02	Make it so that all thread contexts are registered with the System, even in	Lisa Hsu
2008-11-02	make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered	Lisa Hsu
2007-08-26	Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.	Gabe Black
2007-07-23	Major changes to how SimObjects are created and initialized. Almost all	Nathan Binkert
2006-12-20	Initial work to make remote gdb available in SE mode. This is completely unte...	Gabe Black
2006-11-06	Remote GDB support has been changed to use inheritance. Alpha should work, bu...	Gabe Black
2006-10-11	since memoryMode was put into the System (from SimObject), things got broken ...	Lisa Hsu
2006-09-30	Merge ktlim@zamp:./local/clean/o3-merge/m5	Kevin Lim
2006-08-15	fixes for gcc 4.1	Ali Saidi
2006-08-15	Some touchup to the reorganized includes and "using" directives.	Gabe Black
2006-07-13	add system.mem_mode = ['timing', 'atomic']	Ali Saidi
2006-07-12	memory mode information now contained in system object	Ali Saidi
2006-06-11	Merge iceaxe.:/Volumes/work/research/m5/head	Nathan Binkert
2006-06-06	Change ExecContext to ThreadContext. This is being renamed to differentiate ...	Kevin Lim
2006-05-31	Updated Authors from bk prs info	Ali Saidi
2006-05-22	New directory structure:	Steve Reinhardt