gem5 - gem5

Age	Commit message (Expand)	Author
2014-05-09	arch, arm: Preserve TLB bootUncacheability when switching CPUs	Geoffrey Blake
2013-06-03	arch: Create a method to finalize physical addresses	Andreas Sandberg
2013-01-07	arch: Add support for invalidating TLBs when draining	Andreas Sandberg
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-09-25	ARM: Squash outstanding walks when instructions are squashed.	Ali Saidi
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2011-02-11	O3: Enhance data address translation by supporting hardware page table walkers.	Giacomo Gabrielli
2011-02-03	Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.	Gabe Black
2010-12-07	ARM: Support switchover with hardware table walkers	Ali Saidi
2010-09-13	Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.	Gabe Black
2009-04-08	tlb: More fixing of unified TLB	Nathan Binkert
2009-04-08	tlb: Don't separate the TLB classes into an instruction TLB and a data TLB	Gabe Black
2009-02-25	CPU: Implement translateTiming which defers to translateAtomic, and convert t...	Gabe Black
2009-02-25	ISA: Replace the translate functions in the TLBs with translateAtomic.	Gabe Black
2008-02-26	TLB: Make a TLB base class and put a virtual demapPage function in it.	Gabe Black
2007-08-30	params: Deprecate old-style constructors; update most SimObject constructors.	Miles Kaufmann
2007-08-28	Address translation: De-templatize the GenericTLB class.	Gabe Black
2007-08-27	Address Translation: Make the Generic TLB only compile in SE mode.	Gabe Black
2007-08-26	Address translation: Make the page table more flexible.	Gabe Black
2007-08-26	Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.	Gabe Black