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AgeCommit message (Expand)Author
2014-09-03sim: Fix checkpoint restore for TickedAndrew Bardsley
2014-09-03arch: Cleanup unused ISA traits constantsAndreas Hansson
2014-08-28mem: adding architectural page table support for SE modeAlexandru
2014-04-01mem: adding a multi-level page table classAlexandru
2014-02-05sim: bump checkpoint version for multiple event queuesCurtis Dunham
2014-08-13sim: remove kernel mapping check for baremetal workloadsDam Sunwoo
2014-08-13cpu: Don't forward declare RefCountingPtrAndreas Sandberg
2014-08-10config: Add SubSystem container for simobjectsGeoffrey Blake
2014-07-23cpu: `Minor' in-order CPU modelAndrew Bardsley
2014-07-19syscall emulation: fix fast build issueSteve Reinhardt
2014-07-18sim: remove unused MemoryModeStrings arraySteve Reinhardt
2014-07-18syscall emulation: fix DPRINTF arg ordering bugSteve Reinhardt
2014-07-01util: Add DVFS perfLevel to checkpoint upgrade scriptRadhika Jagtap
2014-06-30power: Add basic DVFS support for gem5Stephan Diestelhorst
2014-06-09sim: More rigorous clocking commentsJoel Hestness
2014-05-12syscall emulation: clean up & comment SyscallReturnSteve Reinhardt
2014-04-17sim, arm: implement more of the at variety syscallsAli Saidi
2014-05-09cpu: Allow setWhen on trace objectsAndrew Bardsley
2014-05-09arch, arm: Preserve TLB bootUncacheability when switching CPUsGeoffrey Blake
2014-04-23sim: Use correct unit for abort messageAndreas Hansson
2014-04-19ruby: recorder: Fix (de-)serializing with different cache block-sizesMarco Elver
2014-04-03sim: Add the ability to lock and migrate between event queuesAndreas Sandberg
2014-03-07scons: Fixes uninitialized warnings issued by clangMitch Hayenga
2014-03-06sim: Schedule the global sync event at curTick() + simQuantumAndreas Sandberg
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2014-01-24sim: Add openat/fstatat syscalls and fix mremapChris Adeniyi-Jones
2014-01-24base: add support for probe points and common probesMatt Horsnell
2014-01-24sim: Expose the current voltage for each object as a statAndreas Hansson
2014-01-24sim: Expose the current clock period as a statAndreas Hansson
2013-12-29sim: Add support for dynamic frequency scalingChristopher Torng
2013-11-29base: Fix race in PollQueue and remove SIGALRM workaroundAndreas Sandberg
2013-11-29base: Clean up signal handlingAndreas Sandberg
2013-11-26sim: correct ticksToCycles() function.Nilay Vaish
2013-11-25sim: simulate with multiple threads and event queuesSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2013-11-12sim: fix event priority name for debug-start optionAnthony Gutierrez
2013-11-01sim: Clarify the difference between tracing and debuggingAndreas Hansson
2013-10-31ARM: add support for TEEHBR accessChander Sudanthi
2013-10-31dev: Fix race conditions in IDE device on newer kernelsGeoffrey Blake
2013-10-31sim: added option to serialize SimLoopExitEventDam Sunwoo
2013-09-18sim: Fix undefined behavior in the pseudo-inst interfaceAndreas Sandberg
2013-09-05sim: Fix clang warning for unused variableAndreas Hansson
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
2013-09-04arch: Header clean up for NOISA resurrectionAndreas Hansson
2013-09-04alpha: Move system virtProxy to Alpha onlyAndreas Hansson
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
2013-08-07x86: add tlb checkpointingNilay Vaish
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-06-27config: Add a system clock command-line optionAkash Bagdia
2013-06-11sim: Revert [34e3295b0e39] (sim: Fix early termination in mult...)Andreas Sandberg
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