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2019-01-10sim-se, arch-arm: Add support for getdents64Javier Setoain
Change-Id: Ib27950144d4c9802ffb842db98aec9e433ccbfc5 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15438 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-01-10sim-se: Refactor clone to avoid most ifdefsAndreas Sandberg
Some parts of clone are architecture dependent. In some cases, we are able to use architecture-specific helper functions or register aliases. However, there is still some architecture-specific that is protected by ifdefs in the common clone implementation. Move these architecture-specific bits to the architecture-specific OS class instead to avoid these ifdefs and make the code a bit more readable. Change-Id: Ia0903d738d0ba890863bddfa77e3b717db7f45de Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15435 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-01-10sim-se: Correctly calculate next PC in cloneAndreas Sandberg
The clone syscall doesn't propagate all state in the PCState object when calculating the return PC of a newly created process. Instead of creating a new PCState object from the next PC address, copy the old PC and advance it. Change-Id: Ice53831920bcb5d198865169ed2cca8d06e37cfe Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15417 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-01-10sim-se: Use CONFIG_CLONE_BACKWARDS for ArmAndreas Sandberg
Linxu on Arm users the CLONE_BACKWARDS argument order for the clone syscall. Change-Id: I48deb4f03140c9d4ef7a89e3e33813e76777f999 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15416 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-12-05arch-x86: Add sys/syscall.h to x86 process.cc/syscall_emul.ccTony Gutierrez
Change a66d12c guards the selection of getdents() in x86's process.cc file with SYS_getdents, however process.cc does not include the right header for SYS_getdents, which leads to x86 choosing the unimplemented call. This change adds sys/syscall.h to address the problem. This change also adds sys/syscall.hh to syscall_emu.cc, which only includes syscall.hh and may not be supported on all systems. Change-Id: If1adcf41e9e455de5f2827ba98c542fdcacdc22e Reviewed-on: https://gem5-review.googlesource.com/c/14775 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-12-04base, sim: Add missing destructorsNikos Nikoleris
Derived classes with virtual functions need to define a virtual destructor or a protected destructor otherwise calling the base class destructor has undefined behavior. This change adds a virtual distructor in the base class. Change-Id: I1c855aa56dff6585ff99b9147bdb4eb9729a0a53 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14815 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-27sim-se: only implement getdentsFunc on supported hostsCiro Santilli
The implementation of the getdents syscall relies on SYS_getdents, which is not available on all archs, because the getdents syscall has been superseded by getdents64, and does not exist on newer archs such as aarch64. This leads the build to break on aarch64 hosts with error: error: 'SYS_getdents' was not declared in this scope Change-Id: I8701fb5b61c0418b14a9463ef135a391a7f7a9ba Reviewed-on: https://gem5-review.googlesource.com/c/14596 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-11-20sim: Deschedule existing events when destructing an event queue.Gabe Black
Other objects in the simulation may try to deschedule their events when destructed, and if they're cleaned up after the event queue is then they might try to deschedule events on an event queue that no longer exists. Change-Id: I9452ce52fba78297ce3dc4b3884289b5e2f2574d Reviewed-on: https://gem5-review.googlesource.com/c/14400 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-11-14sim: Move BitUnion overloading to show/parseParamsGiacomo Travaglini
This patch is moving template overloading for BitUnions into the showParam, parseParams functions. Henceforth BitUnion types will use the common param wrapper. This patch implicitly implements (UN)SERIALIZE_CONTAINER for BitUnions. Change-Id: I0e1faadb4afd4dc9de5dc5fca40041e349c9ba73 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13636 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-14sim: Move paramIn/Out definition to header fileGiacomo Travaglini
This patch is moving the definitions of paramIn/Out templates to the header file. In this way we gain: 1) We don't have to do explicit instantiation anymore for user defined types. This spares us from including data type header files into serialize.cc 2) We can overload show/parseParam for BitUnions or any other type that requires special handling when serializing. Just by overloading the two templates we get all the containers' (list, vector, array..) serialization for free 2) gtest: With the idea of adding unit tests for Serializable objects, we can avoid importing serialize.cc and just redefine Serializable methods in the test source, implementing a Serializable stub Change-Id: I45a9bb87d5ef886a3668fd477005cd105f612e36 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13635 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-12sim: Push the global frequency management code into C++.Gabe Black
That makes it available when python is left out, and makes it available to c++ code without having to call back into python. Change-Id: If82e7e8eff526f2b957f84afe046e1d56fed4aa2 Reviewed-on: https://gem5-review.googlesource.com/c/14055 Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-30syscall_emul: fix openat when directory does not end in "/"Ciro Santilli
Before this commit, the following code: dir_fd = open(".", O_DIRECTORY); file_fd = openat(dir_fd, "ble", O_CREAT, S_IRUSR | S_IWUSR); would create a file called ".ble" in the current working directory, instead of the correct "ble". Change-Id: I1525a088d49744e29b760387afabef9f1ac98646 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13005 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-10-01sim: Extend (UN)SERIALIZE_ARRAY to BitUnionsGiacomo Travaglini
This patch is making it possible to use SERIALIZE_ARRAY and UNSERIALIZE array for serializing arrays of BitUnions. Change-Id: I682766b472585f70a89338f373fb94dff5db53c3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12924 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-09-19syscall_emul: implement dir-related syscallsBrandon Potter
Add getdents, rmdir, chdir, and mknod to SE mode for x86. Change-Id: I387ea3066869e8999bc0064f74070f4e47c1e9a1 Reviewed-on: https://gem5-review.googlesource.com/12112 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-09-19syscall_emul: refactor FDEntry and children classesBrandon Potter
Strips off superfluous inline specifiers in header file. Changes return types and parameters that deal with strings to include the const& specifiers. Change-Id: I570b1801abb059b91216f0223458d00963b9ca1c Reviewed-on: https://gem5-review.googlesource.com/12111 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-19syscall_emul: style changes and FDArray refactorBrandon Potter
Some members were defined as public when they should have been privately declared so these were moved to the appropriate spot. The operator[] had inline specified for for an in-class definition which is redundant since inline definitions are always implicitly inline. Private members had the leading underscore applied to them to denote that they're private (consistent with style guide). Changed static const defined class variable into a constexpr with brace-list initialization. Change-Id: If3054416b57827d1542e9ebab428d67d0e767723 Reviewed-on: https://gem5-review.googlesource.com/12110 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-19syscall_emul: expand AuxVector classBrandon Potter
The AuxVector class is responsible for holding Process data. The data that it holds is normally setup by an OS kernel in the process address space. The purpose behind doing this is to pass in information that the process will need for various reasons. (Check out the enum in the header file for an idea of what the AuxVector holds.) The AuxVector struct was changed into a class and encapsulation methods were added to protect access to the member variables. The host ISA may have a different endianness than the simulated ISA. Since data is passed between the process address space and the simulator for auxiliary vectors, we need to worry about maintaining endianness for the right context. Change-Id: I32c5ac4b679559886e1efeb4b5483b92dfc94af9 Reviewed-on: https://gem5-review.googlesource.com/12109 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-09-14power: Add a clock_period variable to power expressionsSherif Elhabbal
Currently 'Clock period in ticks' stat is not accessible in power equations . This patch adds a variable 'clock_period' to be referenced to get the Clock period in ticks Signed-off-by: Sherif Elhabbal <elhabbalsherif@gmail.com> Change-Id: Icac6a2e2003ed75d1680180e53343b0203139d72 Reviewed-on: https://gem5-review.googlesource.com/12664 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-11base: Correct a small typo in sim/core.(hh|cc).Gabe Black
The value GHz with a small z was spelled GHZ with a large z, which was inconsistent with the other frequency-like values in that namespace. Change-Id: I55dfc447a5811ae584e46769cd9cadd08bd1e716 Reviewed-on: https://gem5-review.googlesource.com/12572 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-07sim: Add System method for MasterID lookupGiacomo Travaglini
A new method (lookupMasterId) has been added to the System. A client should use it when querying the System for the MasterID of a particular master. It changes from getMasterId since it is not registering a new MasterID if the master is not found in the master's list. Change-Id: I701158d22e235085bba9ab91154fbb702cae1467 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11969 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-06-25syscall_emul: adding symlink system callMatt Sinclair
Change-Id: Iebda05c130b4d2ee8434cad1e703933bfda486c8 Reviewed-on: https://gem5-review.googlesource.com/11490 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-06-25syscall_emul: adding link system callMatt Sinclair
Change-Id: If8922c2233bbe1f6fce35f64d1a44b91d2cfeed2 Reviewed-on: https://gem5-review.googlesource.com/11489 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-05-30dev: Exit correctly in dist-gem5 for SE modeMichael LeBeane
Do not allow the exit() syscall to terminate gem5 when running in dist-gem5 mode. The exit must be coordinated by the distributed interface instead. Change-Id: I57f47610b59fe9e18ba3a1667fb5e45cecac1a81 Reviewed-on: https://gem5-review.googlesource.com/10461 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Mohammad Alian <m.alian1369@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-05-16style: fix amd license and style issuesTony Gutierrez
Change-Id: I26136fb49f743c4a597f8021cfd27f78897267b5 Reviewed-on: https://gem5-review.googlesource.com/10463 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-05-09sim: Remove trailing dot when assigning a master's nameGiacomo Travaglini
This patch fixes the master's name allocation in the system. The error was occurring when a submaster was not specified in getMasterId: a trailing separation dot was still added to the master's name. Change-Id: I0e67900f6fdd36a61900453b55219fc7007d1b05 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10301 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-04-27sim,cpu,mem,arch: Introduced MasterInfo data structureGiacomo Travaglini
With this patch a gem5 System will store more info about its Masters. While it was previously keeping track of the Master name and Master ID only, it is now adding a per-Master pointer to the SimObject related to the Master. This will make it possible for a client to query a System for a Master using either the master's name or the master's pointer. Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9781 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-20docs: Fix power model doxygenJason Lowe-Power
Change-Id: I0a9a30bc4a89411e0f1dd897f0d1f05f20790b50 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/9981 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-03-15sim-se: Fix fallthrough in prlimitJason Lowe-Power
Change-Id: Ieec4651000b3b4de05ba5ba11fdfa5392a5477e7 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8904 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-02-28sim, power: Temperature used for power calculationsAnouk Van Laer
The temperature used for the power calculations was fixed at 0 degrees, unless a thermal model was setup. This commit allows the user to set the temperature that needs to be used by the power calculation during gem5 configuration. This value will be overwritten if there are thermal models present. Change-Id: I7ca8fa6766bdcba9d362c12fc75d1e1f74385f35 Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8602 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-28sim: Added model type to power modelAnouk Van Laer
Static, dynamic or all to differentiate between types of power models so for example static models will not be asked for a dynamic power Change-Id: I3a0385821f7c671aedddaebeb038c677367faa81 Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8601 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-16sim: Add gtoh/htog helpers that take an explicit endiannessChuan Zhu
Add helper functions to swap between guest byte order and host byte order that take a guest endianness as a parameter. These functions are called htog and htog to be consistent with the helper functions that extract guest byte order from a compile time constant. Change-Id: Ie6be7dfd3b7a58ad6bfb57b25be5f85b5f425929 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8201 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-02-09sim: Remove _numContexts member in System classGiacomo Travaglini
A System object has a _numContexts member variable which represent the number of ThreadContext registered in the System. Since this has to match the size of the ThreadContext vector, this patch removes the manually cached size. This was usually used as a for-loop index, whereas we want to enforce the use of range-based loops whenever possible. Change-Id: I1ba317c0393bcc9c1aeebbb1fc22d7b2bc2cf90c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8062 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-01-29arm: DT autogeneration - Device Tree generation methodsGlenn Bergmans
This patch adds an extra layer to the pyfdt library such that usage gets easier and device tree nodes can be specified in less code, without limiting original usage. Note to not import both the pyfdt and fdthelper in the same namespace (but generally fdthelper is all you need, because it supplies the same classes even when they are not extended in any way) Also, this patch lays out the primary functionality for generating a device tree, where every SimObject gets an empty generateDeviceTree method and ArmSystems loop over their children in an effort to merge all the nodes. Devices are implemented in other patches. Change-Id: I4d0a0666827287fe42e18447f19acab4dc80cc49 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5962 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-23tarch, mem: Abstract the data stored in the SE page tables.Gabe Black
Rather than store the actual TLB entry that corresponds to a mapping, we can just store some abstracted information (address, a few flags) and then let the caller turn that into the appropriate entry. There could potentially be some small amount of overhead from creating entries vs. storing them and just installing them, but it's likely pretty minimal since that only happens on a TLB miss (ideally rare), and, if it is problematic, there could be some preallocated TLB entries which are just minimally filled in as necessary. This has the nice effect of finally making the page tables ISA agnostic. Change-Id: I11e630f60682f0a0029b0683eb8ff0135fbd4317 Reviewed-on: https://gem5-review.googlesource.com/7350 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-23x86, mem: Rewrite the multilevel page table class.Gabe Black
The new version extracts all the x86 specific aspects of the class, and builds the interface around a variable collection of template arguments which are classes that represent the different levels of the page table. The multilevel page table class is now much more ISA independent. Change-Id: Id42e168a78d0e70f80ab2438480cb6e00a3aa636 Reviewed-on: https://gem5-review.googlesource.com/7347 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-20sim: Use the new BitUnion templates in serialize.hh.Gabe Black
serialize.hh should not reference internal implementation details in the underlying BitUnion types. Change-Id: I1ce29243db63801b7788f037fdc54811bdab889c Reviewed-on: https://gem5-review.googlesource.com/7203 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-01-20base: Rework bitunions so they can be more flexible.Gabe Black
They are now oriented around a class which makes it easy to provide custom setter/getter functions which let you set or read bits in an arbitrary way. Future additions may add the ability to add custom bitfield methods, and index-able bitfields. Change-Id: Ibd6d4d9e49107490f6dad30a4379a8c93bda9333 Reviewed-on: https://gem5-review.googlesource.com/7201 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-20sim, arch, base: Refactor the base remote GDB class.Gabe Black
Fold the GDBListener class into the main BaseRemoteGDB class, move around a bunch of functions, convert a lot of internal functions to be private, move some functions into the .cc, make some functions non-virtual which didn't really need to be overridden. Change-Id: Id0832b730b0fdfb2eababa5067e72c66de1c147d Reviewed-on: https://gem5-review.googlesource.com/7422 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-19arch, mem, sim: Consolidate and rename the SE mode page table classes.Gabe Black
Now that Nothing inherits from PageTableBase directly, it can be merged into FuncPageTable. This change also takes the opportunity to rename the combined class to EmulationPageTable which lets you know that it's specifically for SE mode. Also remove the page table entry cache since it doesn't seem to actually improve performance. The TLBs likely absorb the majority of the locality, essentially acting like a cache like they would in real hardware. Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13 Reviewed-on: https://gem5-review.googlesource.com/7342 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-16sim: Simplify registerThreadContext a little bit.Gabe Black
The code in this function was a little convoluted. This change attempts to simplify it a little bit to make it easier to read. Change-Id: I1ae557b9fede47fa89a9ea550bd0af8ad242449f Reviewed-on: https://gem5-review.googlesource.com/7421 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-11arch,mem: Move page table construction into the arch classes.Gabe Black
This gets rid of an awkward NoArchPageTable class, and also gives the arch a place to inject ISA specific parameters (specifically page size) without having to have TheISA:: in the generic version of these types. Change-Id: I1412f303460d5c43dafdb9b3cd07af81c908a441 Reviewed-on: https://gem5-review.googlesource.com/6981 Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-10arch-riscv,sim: Support clone syscall in RISC-VTuan Ta
(1) This patch sets a correct order of clone syscall's arguments for RISC-V. Linux kernel 4.15 uses CLONE_BACKWARDS flag by default for RISC-V. The flag in the Linux kernel defines the list of clone syscall's arguments in the following order: clone_flags (flags) newsp (newStack) parent_tidptr (ptidPtr) tls (tlsPtr) child_tidptr (ctidPtr) Code reference: https://github.com/riscv/riscv-linux/blob/master/kernel/fork.c https://github.com/riscv/riscv-linux/blob/master/arch/riscv/Kconfig (2) This patch copies a parent thread's register values to its child thread in clone syscall. Change-Id: I2eb1c8e80990861080ce7153503ed784fb2c7bdf Reviewed-on: https://gem5-review.googlesource.com/6904 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
2018-01-05sim: Fix a bug in prlimit syscall in SE modeTuan Ta
The old_limit pointer is supposed to be the 4th argument (index 3) of the prlimit syscall. This patch sets old_limit pointer to the correct argument. Change-Id: I97808f7234cd2622cb3eb2f1e0beb7fc8cf492c1 Reviewed-on: https://gem5-review.googlesource.com/6903 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2017-12-14misc: Updates for gcc7.2 for x86Jason Lowe-Power
GCC 7.2 is much stricter than previous GCC versions. The following changes are needed: * There is now a warning if there is an implicit fallthrough between two case statments. C++17 adds the [[fallthrough]]; declaration. However, to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH. M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and if that doesn't exist, it defaults to nothing (no older compilers generate warnings). * The above resulted in a couple of bugs that were found. This is noted in the review request on gerrit. * throw() for dynamic exception specification is deprecated * There were a couple of new uninitialized variable warnings * Can no longer perform bitwise operations on a bool. * Must now include <functional> for std::function * Compiler bug for void* lambda. Changed to auto as work around. See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878 Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5802 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-12-13arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.Gabe Black
Replace them with std::array<>s. Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34 Reviewed-on: https://gem5-review.googlesource.com/6602 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-13base: Add endianness conversion functions for std::array types.Gabe Black
These swap the endianness of each element within the array individually. They probably obsolute the Twin(32|64)_t types which I believe were used for SPARC. Change-Id: Ic389eb24bdcdc0081068b0c5a37abdf416f6c924 Reviewed-on: https://gem5-review.googlesource.com/6581 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-04misc: Rename misc.(hh|cc) to logging.(hh|cc)Gabe Black
These files aren't a collection of miscellaneous stuff, they're the definition of the Logger interface, and a few utility macros for calling into that interface (panic, warn, etc.). Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1 Reviewed-on: https://gem5-review.googlesource.com/6226 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-11-27scons: Switch from "guards" to "tags" on source files.Gabe Black
Tags are just arbitrary strings which are attached to source files which mark them as having some property. By default, all source files have the "gem5 lib" tag added to them which marks them as part of the gem5 library, the primary component of the gem5 binary but also a seperable component for use in, for example, system C. The tags can be completely overridden by setting the "tags" parameter on Source, etc., functions, and can be augmented by setting "add_tags" which are tags that will be added, or alternatively additional tags. It's possible to specify both, in which case the tags will be set to the union of tags and add_tags. add_tags is supposed to be a way to add extra tags to the default without actually overriding the default. Both tags and add_tags can be a list/tuple/etc of tags, or a single string which will be converted into a set internally. Other existing tags include: 1. "python" for files that need or are used with python and are excluded when the --without-python option is set 2. "main" for the file(s) which implement the gem5 binary's main function. 3. The name of a unit test to group its files together. 4. Tags which group source files for partial linking. By grouping the "tags" into a single parameter instead of taking all extra parameters as tags, the extra parameters can, in the future, be passed to the underlying scons environment. Also, the tags are either present or not. With guards, they could be present and True, present and False, or not present at all. Change-Id: I6d0404211a393968df66f7eddfe019897b6573a2 Reviewed-on: https://gem5-review.googlesource.com/5822 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-22sim-se: Add default to SyscallDesc constructorAlec Roelke
This patch adds a default value of unimplementedFunc to SyscallDesc's constructor's second argument, which makes adding system call placeholders to SE mode cleaner. Change-Id: I3e7efb3a887cc52d16d2095d3dd2e2a96fb882fb Reviewed-on: https://gem5-review.googlesource.com/5501 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2017-11-21sim: Fix need to save address space info during serialization.Austin Harris
This fixes a fatal already mapped error in FuncPageTable::allocate that occurs in some cases when restoring from a checkpoint. Change-Id: Ib726a69358118626663e42b7f14889b0d3a98de0 Reported-by: Ruohuang Zheng <zhengruohuang@gmail.com> Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/5901 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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