gem5 - gem5

Age	Commit message (Expand)	Author
2013-03-02	sim: remove duplicate check on stack size	Nilay Vaish
2013-02-19	scons: Add warning for missing declarations	Andreas Hansson
2013-02-19	scons: Fix up numerous warnings about name shadowing	Andreas Hansson
2013-02-19	sim: Make clock private and access using clockPeriod()	Andreas Hansson
2013-02-15	sim: Add a system-global option to bypass caches	Andreas Sandberg
2013-01-31	sim: remove unused struct priority_compare	Nilay Vaish
2013-01-08	util: add m5_fail op.	Lluís Vilanova
2013-01-08	sim: Fix early termination in multi-core simulation under SE mode.	Tao Zhang
2013-01-08	arm: add access syscall for ARM SE mode	Mitch Hayenga
2013-01-07	stats: Fix swig wrapping for Tick in stats	Sascha Bischoff
2013-01-07	sim: Remove unused variables	Andreas Sandberg
2013-01-07	arm: Remove the register mapping hack used when copying TCs	Andreas Sandberg
2013-01-07	arch: Move the ISA object to a separate section	Andreas Sandberg
2013-01-07	arch: Add support for invalidating TLBs when draining	Andreas Sandberg
2013-01-07	sim: Fatal if a clocked object is set to have a clock of 0	Andreas Hansson
2013-01-07	config: Do not use hardcoded physmem in fs script	Andreas Hansson
2013-01-07	base: Add wrapped protobuf output streams	Andreas Hansson
2013-01-04	SPARC: Keep a copy of the current ASI in the decoder.	Gabe Black
2012-11-16	sim: have a curTick per eventq	Nilay Vaish
2012-11-02	sim: Add drain methods to request additional cleanup operations	Andreas Sandberg
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-11-02	ARM: dump stats and process info on context switches	Dam Sunwoo
2012-11-02	sim: Fix as issue where exit events on instr queues are used after freed.	Ali Saidi
2012-10-25	dev: Make default clock more reasonable for system and devices	Andreas Hansson
2012-10-15	ruby: reset timing after cache warm up	Nilay Vaish
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-10-15	Mem: Separate the host and guest views of memory backing store	Andreas Hansson
2012-10-15	Checkpoint: Make system serialize call children	Andreas Hansson
2012-10-15	Clock: Inherit the clock from parent by default	Andreas Hansson
2012-09-25	Statistics: Add a function to configure periodic stats dumping	Sascha Bischoff
2012-09-25	ARM: Squash outstanding walks when instructions are squashed.	Ali Saidi
2012-09-25	sim: Move CPU-specific methods from SimObject to the BaseCPU class	Andreas Sandberg
2012-09-25	sim: Remove SimObject::setMemoryMode	Andreas Sandberg
2012-09-21	SE: Ignore FUTEX_PRIVATE_FLAG of sys_futex	Lluc Alvarez
2012-09-10	NetBSD: Build on NetBSD	Palle Lyckegaard
2012-09-07	sim: Update the SimObject documentation	Andreas Sandberg
2012-09-07	sim: Remove the unused SimObject::regFormulas method	Andreas Sandberg
2012-09-07	sim: add validation to make sure there is memory where we're loading the kernel	Krishnendra Nathella
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-08-28	Clock: Rework clocks to avoid tick-to-cycle transformations	Andreas Hansson
2012-08-27	sim: fix overflow check in simulate because Tick is now unsigned	Anthony Gutierrez
2012-08-27	System: Remove redundant call to startupCPU	Nilay Vaish
2012-08-21	EventManager: Remove test for NULL pointer in constructor	Andreas Hansson
2012-08-21	Clock: Make Tick unsigned and remove UTick	Andreas Hansson
2012-08-21	Clock: Move the clock and related functions to ClockedObject	Andreas Hansson
2012-08-15	O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...	Anthony Gutierrez
2012-08-08	System: set kernel to null, if unspecified.	Nilay Vaish
2012-08-06	process: add progName() virtual function	Steve Reinhardt
2012-08-06	syscall_emul: clean up open() code a bit.	Steve Reinhardt