gem5 - gem5

Age	Commit message (Expand)	Author
2014-09-09	misc: Fix a number of unitialised variables and members	Andreas Hansson
2014-04-29	arm: use condition code registers for ARM ISA	Curtis Dunham
2014-09-03	sim: Fix checkpoint restore for Ticked	Andrew Bardsley
2014-09-03	arch: Cleanup unused ISA traits constants	Andreas Hansson
2014-08-28	mem: adding architectural page table support for SE mode	Alexandru
2014-04-01	mem: adding a multi-level page table class	Alexandru
2014-02-05	sim: bump checkpoint version for multiple event queues	Curtis Dunham
2014-08-13	sim: remove kernel mapping check for baremetal workloads	Dam Sunwoo
2014-08-13	cpu: Don't forward declare RefCountingPtr	Andreas Sandberg
2014-08-10	config: Add SubSystem container for simobjects	Geoffrey Blake
2014-07-23	cpu: `Minor' in-order CPU model	Andrew Bardsley
2014-07-19	syscall emulation: fix fast build issue	Steve Reinhardt
2014-07-18	sim: remove unused MemoryModeStrings array	Steve Reinhardt
2014-07-18	syscall emulation: fix DPRINTF arg ordering bug	Steve Reinhardt
2014-07-01	util: Add DVFS perfLevel to checkpoint upgrade script	Radhika Jagtap
2014-06-30	power: Add basic DVFS support for gem5	Stephan Diestelhorst
2014-06-09	sim: More rigorous clocking comments	Joel Hestness
2014-05-12	syscall emulation: clean up & comment SyscallReturn	Steve Reinhardt
2014-04-17	sim, arm: implement more of the at variety syscalls	Ali Saidi
2014-05-09	cpu: Allow setWhen on trace objects	Andrew Bardsley
2014-05-09	arch, arm: Preserve TLB bootUncacheability when switching CPUs	Geoffrey Blake
2014-04-23	sim: Use correct unit for abort message	Andreas Hansson
2014-04-19	ruby: recorder: Fix (de-)serializing with different cache block-sizes	Marco Elver
2014-04-03	sim: Add the ability to lock and migrate between event queues	Andreas Sandberg
2014-03-07	scons: Fixes uninitialized warnings issued by clang	Mitch Hayenga
2014-03-06	sim: Schedule the global sync event at curTick() + simQuantum	Andreas Sandberg
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2014-01-24	sim: Add openat/fstatat syscalls and fix mremap	Chris Adeniyi-Jones
2014-01-24	base: add support for probe points and common probes	Matt Horsnell
2014-01-24	sim: Expose the current voltage for each object as a stat	Andreas Hansson
2014-01-24	sim: Expose the current clock period as a stat	Andreas Hansson
2013-12-29	sim: Add support for dynamic frequency scaling	Christopher Torng
2013-11-29	base: Fix race in PollQueue and remove SIGALRM workaround	Andreas Sandberg
2013-11-29	base: Clean up signal handling	Andreas Sandberg
2013-11-26	sim: correct ticksToCycles() function.	Nilay Vaish
2013-11-25	sim: simulate with multiple threads and event queues	Steve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2013-11-12	sim: fix event priority name for debug-start option	Anthony Gutierrez
2013-11-01	sim: Clarify the difference between tracing and debugging	Andreas Hansson
2013-10-31	ARM: add support for TEEHBR access	Chander Sudanthi
2013-10-31	dev: Fix race conditions in IDE device on newer kernels	Geoffrey Blake
2013-10-31	sim: added option to serialize SimLoopExitEvent	Dam Sunwoo
2013-09-18	sim: Fix undefined behavior in the pseudo-inst interface	Andreas Sandberg
2013-09-05	sim: Fix clang warning for unused variable	Andreas Hansson
2013-09-04	arch: Resurrect the NOISA build target and rename it NULL	Andreas Hansson
2013-09-04	arch: Header clean up for NOISA resurrection	Andreas Hansson
2013-09-04	alpha: Move system virtProxy to Alpha only	Andreas Hansson
2013-08-19	power: Add voltage domains to the clock domains	Akash Bagdia
2013-08-07	x86: add tlb checkpointing	Nilay Vaish
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2013-06-27	sim: Add the notion of clock domains to all ClockedObjects	Akash Bagdia