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AgeCommit message (Expand)Author
2018-01-23tarch, mem: Abstract the data stored in the SE page tables.Gabe Black
2018-01-23x86, mem: Rewrite the multilevel page table class.Gabe Black
2018-01-20sim: Use the new BitUnion templates in serialize.hh.Gabe Black
2018-01-20base: Rework bitunions so they can be more flexible.Gabe Black
2018-01-20sim, arch, base: Refactor the base remote GDB class.Gabe Black
2018-01-19arch, mem, sim: Consolidate and rename the SE mode page table classes.Gabe Black
2018-01-16sim: Simplify registerThreadContext a little bit.Gabe Black
2018-01-11arch,mem: Move page table construction into the arch classes.Gabe Black
2018-01-10arch-riscv,sim: Support clone syscall in RISC-VTuan Ta
2018-01-05sim: Fix a bug in prlimit syscall in SE modeTuan Ta
2017-12-14misc: Updates for gcc7.2 for x86Jason Lowe-Power
2017-12-13arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.Gabe Black
2017-12-13base: Add endianness conversion functions for std::array types.Gabe Black
2017-12-04misc: Rename misc.(hh|cc) to logging.(hh|cc)Gabe Black
2017-11-27scons: Switch from "guards" to "tags" on source files.Gabe Black
2017-11-22sim-se: Add default to SyscallDesc constructorAlec Roelke
2017-11-21sim: Fix need to save address space info during serialization.Austin Harris
2017-11-17sim: Implement load_addr_mask auto-calculationGeoffrey Blake
2017-11-16sim: ScopedMigration does nothing if both eqs are the sameTiago Muck
2017-11-16pwr: Enable multiple power models per componentDavid Guillen Fandos
2017-11-16sim: Clocked object debug message updated for clarityTiago Muck
2017-11-16sim: Add an option to load additional kernel objectsAndreas Sandberg
2017-11-06sim-se: Add prlimit system callAlec Roelke
2017-09-28sim-se: Fix mremap for downward growing mmap regionsRico Amslinger
2017-09-27sim: make compile on FreeBSD prior to 11Bjoern A. Zeeb
2017-09-25mem: Record the request master ID in the PacketInfo structure.Gabe Black
2017-09-21sim: Stop using loadState in the Root SimObject.Gabe Black
2017-08-01sim: Use named constants for pseudo opsAndreas Sandberg
2017-07-20sim: Prevent segfault in the wakeCpu m5op if id is invalidJose Marinho
2017-07-17sim, x86: Make clone a virtual functionSean Wilson
2017-07-12sim, gdb: Refactor some Event subclasses into lambdasSean Wilson
2017-07-12cpu, sim: Add param to force CPUs to wait for GDBJose Marinho
2017-07-10sim: Fix clashing stat names in TickedObject and TickedJose Marinho
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
2017-07-05kvm: move Kvm check from ARM Kvm GIC to SystemCurtis Dunham
2017-06-21sim: Updated ClockedObject power state warningJason Lowe-Power
2017-06-20sim, x86: Replace EventWrapper use with EventFunctionWrapperSean Wilson
2017-06-20sim: Add generic EventFunctionWrapperSean Wilson
2017-06-20sim: Remove DelayFunctionSean Wilson
2017-05-25x86: sim: Make 32 bit x86 processes work again.Gabe Black
2017-05-24sim: Add hooks to implement event reference countingAndreas Sandberg
2017-05-19base, sim, arch: Fix clang 5.0 warningsAndreas Sandberg
2017-05-12syscall_emul: Fix undefined macro behaviorAndreas Sandberg
2017-05-05syscall_emul: Argument retrieval bug fixAlexandru Dutu
2017-05-02base, sim, dev: Remove SWIGAndreas Sandberg
2017-05-02python: Use PyBind11 instead of SWIG for Python wrappersAndreas Sandberg
2017-04-11power: Allow global stats in power equationsStephan Diestelhorst
2017-04-08power: Clarify the unit used for the power equations (W)Stephan Diestelhorst
2017-04-06power: Add a voltage variable to power expressionsAndreas Sandberg
2017-04-06power: Add error checking to MathExprPowerModelAndreas Sandberg