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AgeCommit message (Expand)Author
2018-10-01sim: Extend (UN)SERIALIZE_ARRAY to BitUnionsGiacomo Travaglini
2018-09-19syscall_emul: implement dir-related syscallsBrandon Potter
2018-09-19syscall_emul: refactor FDEntry and children classesBrandon Potter
2018-09-19syscall_emul: style changes and FDArray refactorBrandon Potter
2018-09-19syscall_emul: expand AuxVector classBrandon Potter
2018-09-14power: Add a clock_period variable to power expressionsSherif Elhabbal
2018-09-11base: Correct a small typo in sim/core.(hh|cc).Gabe Black
2018-09-07sim: Add System method for MasterID lookupGiacomo Travaglini
2018-06-25syscall_emul: adding symlink system callMatt Sinclair
2018-06-25syscall_emul: adding link system callMatt Sinclair
2018-05-30dev: Exit correctly in dist-gem5 for SE modeMichael LeBeane
2018-05-16style: fix amd license and style issuesTony Gutierrez
2018-05-09sim: Remove trailing dot when assigning a master's nameGiacomo Travaglini
2018-04-27sim,cpu,mem,arch: Introduced MasterInfo data structureGiacomo Travaglini
2018-04-20docs: Fix power model doxygenJason Lowe-Power
2018-03-15sim-se: Fix fallthrough in prlimitJason Lowe-Power
2018-02-28sim, power: Temperature used for power calculationsAnouk Van Laer
2018-02-28sim: Added model type to power modelAnouk Van Laer
2018-02-16sim: Add gtoh/htog helpers that take an explicit endiannessChuan Zhu
2018-02-09sim: Remove _numContexts member in System classGiacomo Travaglini
2018-01-29arm: DT autogeneration - Device Tree generation methodsGlenn Bergmans
2018-01-23tarch, mem: Abstract the data stored in the SE page tables.Gabe Black
2018-01-23x86, mem: Rewrite the multilevel page table class.Gabe Black
2018-01-20sim: Use the new BitUnion templates in serialize.hh.Gabe Black
2018-01-20base: Rework bitunions so they can be more flexible.Gabe Black
2018-01-20sim, arch, base: Refactor the base remote GDB class.Gabe Black
2018-01-19arch, mem, sim: Consolidate and rename the SE mode page table classes.Gabe Black
2018-01-16sim: Simplify registerThreadContext a little bit.Gabe Black
2018-01-11arch,mem: Move page table construction into the arch classes.Gabe Black
2018-01-10arch-riscv,sim: Support clone syscall in RISC-VTuan Ta
2018-01-05sim: Fix a bug in prlimit syscall in SE modeTuan Ta
2017-12-14misc: Updates for gcc7.2 for x86Jason Lowe-Power
2017-12-13arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.Gabe Black
2017-12-13base: Add endianness conversion functions for std::array types.Gabe Black
2017-12-04misc: Rename misc.(hh|cc) to logging.(hh|cc)Gabe Black
2017-11-27scons: Switch from "guards" to "tags" on source files.Gabe Black
2017-11-22sim-se: Add default to SyscallDesc constructorAlec Roelke
2017-11-21sim: Fix need to save address space info during serialization.Austin Harris
2017-11-17sim: Implement load_addr_mask auto-calculationGeoffrey Blake
2017-11-16sim: ScopedMigration does nothing if both eqs are the sameTiago Muck
2017-11-16pwr: Enable multiple power models per componentDavid Guillen Fandos
2017-11-16sim: Clocked object debug message updated for clarityTiago Muck
2017-11-16sim: Add an option to load additional kernel objectsAndreas Sandberg
2017-11-06sim-se: Add prlimit system callAlec Roelke
2017-09-28sim-se: Fix mremap for downward growing mmap regionsRico Amslinger
2017-09-27sim: make compile on FreeBSD prior to 11Bjoern A. Zeeb
2017-09-25mem: Record the request master ID in the PacketInfo structure.Gabe Black
2017-09-21sim: Stop using loadState in the Root SimObject.Gabe Black
2017-08-01sim: Use named constants for pseudo opsAndreas Sandberg
2017-07-20sim: Prevent segfault in the wakeCpu m5op if id is invalidJose Marinho