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AgeCommit message (Expand)Author
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
2013-09-04arch: Header clean up for NOISA resurrectionAndreas Hansson
2013-09-04alpha: Move system virtProxy to Alpha onlyAndreas Hansson
2013-08-19power: Add voltage domains to the clock domainsAkash Bagdia
2013-08-07x86: add tlb checkpointingNilay Vaish
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-06-27config: Add a system clock command-line optionAkash Bagdia
2013-06-11sim: Revert [34e3295b0e39] (sim: Fix early termination in mult...)Andreas Sandberg
2013-06-03arch: Create a method to finalize physical addressesAndreas Sandberg
2013-06-03sim: Add debug output when executing pseudo-instructionsAndreas Sandberg
2013-05-02sim: Add support for m5fail in pseudoInst()Andreas Sandberg
2013-04-22sim: Add a helper function to execute pseudo instructionsAndreas Sandberg
2013-04-22sim: separate nextCycle() and clockEdge() in clockedObjectsDam Sunwoo
2013-04-22sim: Add helper functions that add PCEvents with custom argumentsAndreas Sandberg
2013-04-17base: load weak symbols from object fileDeyuan Guo ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2013-03-02sim: remove duplicate check on stack sizeNilay Vaish
2013-02-19scons: Add warning for missing declarationsAndreas Hansson
2013-02-19scons: Fix up numerous warnings about name shadowingAndreas Hansson
2013-02-19sim: Make clock private and access using clockPeriod()Andreas Hansson
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-01-31sim: remove unused struct priority_compareNilay Vaish
2013-01-08util: add m5_fail op.Lluís Vilanova
2013-01-08sim: Fix early termination in multi-core simulation under SE mode.Tao Zhang
2013-01-08arm: add access syscall for ARM SE modeMitch Hayenga
2013-01-07stats: Fix swig wrapping for Tick in statsSascha Bischoff
2013-01-07sim: Remove unused variablesAndreas Sandberg
2013-01-07arm: Remove the register mapping hack used when copying TCsAndreas Sandberg
2013-01-07arch: Move the ISA object to a separate sectionAndreas Sandberg
2013-01-07arch: Add support for invalidating TLBs when drainingAndreas Sandberg
2013-01-07sim: Fatal if a clocked object is set to have a clock of 0Andreas Hansson
2013-01-07config: Do not use hardcoded physmem in fs scriptAndreas Hansson
2013-01-07base: Add wrapped protobuf output streamsAndreas Hansson
2013-01-04SPARC: Keep a copy of the current ASI in the decoder.Gabe Black
2012-11-16sim: have a curTick per eventqNilay Vaish
2012-11-02sim: Add drain methods to request additional cleanup operationsAndreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-11-02ARM: dump stats and process info on context switchesDam Sunwoo
2012-11-02sim: Fix as issue where exit events on instr queues are used after freed.Ali Saidi
2012-10-25dev: Make default clock more reasonable for system and devicesAndreas Hansson
2012-10-15ruby: reset timing after cache warm upNilay Vaish
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-10-15Mem: Separate the host and guest views of memory backing storeAndreas Hansson
2012-10-15Checkpoint: Make system serialize call childrenAndreas Hansson
2012-10-15Clock: Inherit the clock from parent by defaultAndreas Hansson
2012-09-25Statistics: Add a function to configure periodic stats dumpingSascha Bischoff
2012-09-25ARM: Squash outstanding walks when instructions are squashed.Ali Saidi
2012-09-25sim: Move CPU-specific methods from SimObject to the BaseCPU classAndreas Sandberg
2012-09-25sim: Remove SimObject::setMemoryModeAndreas Sandberg
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