Age | Commit message (Expand) | Author |
2018-01-16 | sim: Simplify registerThreadContext a little bit. | Gabe Black |
2018-01-11 | arch,mem: Move page table construction into the arch classes. | Gabe Black |
2018-01-10 | arch-riscv,sim: Support clone syscall in RISC-V | Tuan Ta |
2018-01-05 | sim: Fix a bug in prlimit syscall in SE mode | Tuan Ta |
2017-12-14 | misc: Updates for gcc7.2 for x86 | Jason Lowe-Power |
2017-12-13 | arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with. | Gabe Black |
2017-12-13 | base: Add endianness conversion functions for std::array types. | Gabe Black |
2017-12-04 | misc: Rename misc.(hh|cc) to logging.(hh|cc) | Gabe Black |
2017-11-27 | scons: Switch from "guards" to "tags" on source files. | Gabe Black |
2017-11-22 | sim-se: Add default to SyscallDesc constructor | Alec Roelke |
2017-11-21 | sim: Fix need to save address space info during serialization. | Austin Harris |
2017-11-17 | sim: Implement load_addr_mask auto-calculation | Geoffrey Blake |
2017-11-16 | sim: ScopedMigration does nothing if both eqs are the same | Tiago Muck |
2017-11-16 | pwr: Enable multiple power models per component | David Guillen Fandos |
2017-11-16 | sim: Clocked object debug message updated for clarity | Tiago Muck |
2017-11-16 | sim: Add an option to load additional kernel objects | Andreas Sandberg |
2017-11-06 | sim-se: Add prlimit system call | Alec Roelke |
2017-09-28 | sim-se: Fix mremap for downward growing mmap regions | Rico Amslinger |
2017-09-27 | sim: make compile on FreeBSD prior to 11 | Bjoern A. Zeeb |
2017-09-25 | mem: Record the request master ID in the PacketInfo structure. | Gabe Black |
2017-09-21 | sim: Stop using loadState in the Root SimObject. | Gabe Black |
2017-08-01 | sim: Use named constants for pseudo ops | Andreas Sandberg |
2017-07-20 | sim: Prevent segfault in the wakeCpu m5op if id is invalid | Jose Marinho |
2017-07-17 | sim, x86: Make clone a virtual function | Sean Wilson |
2017-07-12 | sim, gdb: Refactor some Event subclasses into lambdas | Sean Wilson |
2017-07-12 | cpu, sim: Add param to force CPUs to wait for GDB | Jose Marinho |
2017-07-10 | sim: Fix clashing stat names in TickedObject and Ticked | Jose Marinho |
2017-07-05 | cpu: Added interface for vector reg file | Rekai Gonzalez-Alberquilla |
2017-07-05 | kvm: move Kvm check from ARM Kvm GIC to System | Curtis Dunham |
2017-06-21 | sim: Updated ClockedObject power state warning | Jason Lowe-Power |
2017-06-20 | sim, x86: Replace EventWrapper use with EventFunctionWrapper | Sean Wilson |
2017-06-20 | sim: Add generic EventFunctionWrapper | Sean Wilson |
2017-06-20 | sim: Remove DelayFunction | Sean Wilson |
2017-05-25 | x86: sim: Make 32 bit x86 processes work again. | Gabe Black |
2017-05-24 | sim: Add hooks to implement event reference counting | Andreas Sandberg |
2017-05-19 | base, sim, arch: Fix clang 5.0 warnings | Andreas Sandberg |
2017-05-12 | syscall_emul: Fix undefined macro behavior | Andreas Sandberg |
2017-05-05 | syscall_emul: Argument retrieval bug fix | Alexandru Dutu |
2017-05-02 | base, sim, dev: Remove SWIG | Andreas Sandberg |
2017-05-02 | python: Use PyBind11 instead of SWIG for Python wrappers | Andreas Sandberg |
2017-04-11 | power: Allow global stats in power equations | Stephan Diestelhorst |
2017-04-08 | power: Clarify the unit used for the power equations (W) | Stephan Diestelhorst |
2017-04-06 | power: Add a voltage variable to power expressions | Andreas Sandberg |
2017-04-06 | power: Add error checking to MathExprPowerModel | Andreas Sandberg |
2017-04-03 | sim: Handle cases where Drainable::resume() creates objects | Andreas Sandberg |
2017-03-17 | syscall-emul: Hotfix for FreeBSD/Mac builds | Brandon Potter |
2017-03-17 | syscall-emul: change NULL to nullptr in Process files | Brandon Potter |
2017-03-09 | style: change NULL to nullptr in syscall files | Brandon Potter |
2017-03-09 | syscall-emul: Rewrite system call exit code | Brandon Potter |
2017-03-09 | syscall-emul: Add the tgkill system call | Brandon Potter |