| Age | Commit message (Expand) | Author |
|---|
| 2018-10-01 | sim: Extend (UN)SERIALIZE_ARRAY to BitUnions | Giacomo Travaglini |
| 2018-09-19 | syscall_emul: implement dir-related syscalls | Brandon Potter |
| 2018-09-19 | syscall_emul: refactor FDEntry and children classes | Brandon Potter |
| 2018-09-19 | syscall_emul: style changes and FDArray refactor | Brandon Potter |
| 2018-09-19 | syscall_emul: expand AuxVector class | Brandon Potter |
| 2018-09-14 | power: Add a clock_period variable to power expressions | Sherif Elhabbal |
| 2018-09-11 | base: Correct a small typo in sim/core.(hh|cc). | Gabe Black |
| 2018-09-07 | sim: Add System method for MasterID lookup | Giacomo Travaglini |
| 2018-06-25 | syscall_emul: adding symlink system call | Matt Sinclair |
| 2018-06-25 | syscall_emul: adding link system call | Matt Sinclair |
| 2018-05-30 | dev: Exit correctly in dist-gem5 for SE mode | Michael LeBeane |
| 2018-05-16 | style: fix amd license and style issues | Tony Gutierrez |
| 2018-05-09 | sim: Remove trailing dot when assigning a master's name | Giacomo Travaglini |
| 2018-04-27 | sim,cpu,mem,arch: Introduced MasterInfo data structure | Giacomo Travaglini |
| 2018-04-20 | docs: Fix power model doxygen | Jason Lowe-Power |
| 2018-03-15 | sim-se: Fix fallthrough in prlimit | Jason Lowe-Power |
| 2018-02-28 | sim, power: Temperature used for power calculations | Anouk Van Laer |
| 2018-02-28 | sim: Added model type to power model | Anouk Van Laer |
| 2018-02-16 | sim: Add gtoh/htog helpers that take an explicit endianness | Chuan Zhu |
| 2018-02-09 | sim: Remove _numContexts member in System class | Giacomo Travaglini |
| 2018-01-29 | arm: DT autogeneration - Device Tree generation methods | Glenn Bergmans |
| 2018-01-23 | tarch, mem: Abstract the data stored in the SE page tables. | Gabe Black |
| 2018-01-23 | x86, mem: Rewrite the multilevel page table class. | Gabe Black |
| 2018-01-20 | sim: Use the new BitUnion templates in serialize.hh. | Gabe Black |
| 2018-01-20 | base: Rework bitunions so they can be more flexible. | Gabe Black |
| 2018-01-20 | sim, arch, base: Refactor the base remote GDB class. | Gabe Black |
| 2018-01-19 | arch, mem, sim: Consolidate and rename the SE mode page table classes. | Gabe Black |
| 2018-01-16 | sim: Simplify registerThreadContext a little bit. | Gabe Black |
| 2018-01-11 | arch,mem: Move page table construction into the arch classes. | Gabe Black |
| 2018-01-10 | arch-riscv,sim: Support clone syscall in RISC-V | Tuan Ta |
| 2018-01-05 | sim: Fix a bug in prlimit syscall in SE mode | Tuan Ta |
| 2017-12-14 | misc: Updates for gcc7.2 for x86 | Jason Lowe-Power |
| 2017-12-13 | arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with. | Gabe Black |
| 2017-12-13 | base: Add endianness conversion functions for std::array types. | Gabe Black |
| 2017-12-04 | misc: Rename misc.(hh|cc) to logging.(hh|cc) | Gabe Black |
| 2017-11-27 | scons: Switch from "guards" to "tags" on source files. | Gabe Black |
| 2017-11-22 | sim-se: Add default to SyscallDesc constructor | Alec Roelke |
| 2017-11-21 | sim: Fix need to save address space info during serialization. | Austin Harris |
| 2017-11-17 | sim: Implement load_addr_mask auto-calculation | Geoffrey Blake |
| 2017-11-16 | sim: ScopedMigration does nothing if both eqs are the same | Tiago Muck |
| 2017-11-16 | pwr: Enable multiple power models per component | David Guillen Fandos |
| 2017-11-16 | sim: Clocked object debug message updated for clarity | Tiago Muck |
| 2017-11-16 | sim: Add an option to load additional kernel objects | Andreas Sandberg |
| 2017-11-06 | sim-se: Add prlimit system call | Alec Roelke |
| 2017-09-28 | sim-se: Fix mremap for downward growing mmap regions | Rico Amslinger |
| 2017-09-27 | sim: make compile on FreeBSD prior to 11 | Bjoern A. Zeeb |
| 2017-09-25 | mem: Record the request master ID in the PacketInfo structure. | Gabe Black |
| 2017-09-21 | sim: Stop using loadState in the Root SimObject. | Gabe Black |
| 2017-08-01 | sim: Use named constants for pseudo ops | Andreas Sandberg |
| 2017-07-20 | sim: Prevent segfault in the wakeCpu m5op if id is invalid | Jose Marinho |
