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2019-05-29arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.Gabe Black
Change-Id: Ia73b2d86a10d02fa09c924a4571477bb5f200eb7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18572 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-21sim-se: change syscall function signatureBrandon Potter
The system calls had four parameters. One of the parameters is ThreadContext and another is Process. The ThreadContext holds the value of the current process so the Process parameter is redundant since the system call functions already have indirect access. With the old API, it is possible to call into the functions with the wrong supplied Process which could end up being a confusing error. This patch removes the redundancy by forcing access through the ThreadContext field within each system call. Change-Id: Ib43d3f65824f6d425260dfd9f67de1892b6e8b7c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12299 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-21sim-se: remove /sys from special pathsTony Gutierrez
Currently, the open system call implementation in SE mode treats /sys/ as a special path that is opened using a special open handler. The ROC runtime, however, reads several files in /sys/ that are supported via path redirection. Here we remove /sys/ from the special files so that the necessary files may be read via path redirection. Change-Id: Ifdab38ea1e6cc486ad43aec96b6e032fe63f137d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12127 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-20sim: Make the Process create function use the object loader mechanism.Gabe Black
This gets rid of the big mass of #if-s around headers and around the code which creates an object file. As a nice side bonus, this also means that in addition to supporting multiple OS/arch combinations simultaneously, the object file loader could support multiple ISAs simultaneously as well, since each could load and set up its object file loaders indepedently and without the base process classes knowledge/involvement. Change-Id: I0a19ad06e30e9062a96d27f00b66756eb3a595ba Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18631 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-18arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.Gabe Black
This code will be preserved through version control, but otherwise creates clutter and will rot in place since it's never compiled. Change-Id: Id265f6deac445116843956ea5cf1210d8127274e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18608 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-06sim-se: correct statfs inclusion on !linux hostAndrea Mondelli
- Added missing header - Fixed typo on __linux__ macro conditional - s/ifdef/if defined/g for consistency Change-Id: I83b69856e5ec8b23b707642c0e14216cf62db31e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18668 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-03sim-se: fix a few bugs/warns from GCC 6Joe Gross
Change-Id: Ib2ad860324fd234b23262d141be3e82628ff61f0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12126 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-05-03sim-se: add eventfd system callBrandon Potter
Change-Id: I7aeb4fe808d0c8f2fb8041e3662d330d8458f09c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12125 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-04-30sim-se: use DPRINTF_SYSCALL for ioctl/wait4Alexandru Dutu
Change-Id: I4fbaf1a0653f13ae964a2574cc26bbaac2dc0686 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12124 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-04-30sim-se: bugfix for 54c77aa055eBrandon Potter
54c77aa055e introduced a bug which manifests as cyclical dependency on a member initialization for the Process class. The current working directory (cwd) parameter is passed into Process to initialize both the target and host versions of the cwd. (The target and host versions may differ if the faux filesystem is used.) The host cwd init invoked methods which rely on the host cwd already being initialized. To avoid the bug, the code will now rely on using the targets cwd version, but will issue checks against the redirect paths. Change-Id: I4ab644a3e00737dbf249f5d6faf20a26ceb04248 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18448 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30arch: cpu: Track kernel stats using the base ISA agnostic type.Gabe Black
Then cast to the ISA specific type when necessary. This removes (mostly) an ISA specific aspect to some of the interfaces. The ISA specific version of the kernel stats still needs to be constructed and stored in a few places which means that kernel_stats.hh still needs to be a switching arch header, for instance. In the future, I'd like to make the kernel its own object like the Process objects in SE mode, and then it would be able to instantiate and maintain its own stats. Change-Id: I8309d49019124f6bea1482aaea5b5b34e8c97433 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18429 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-30sim-se: add socket ioctlsBrandon Potter
The OpenMPI 1.8.2 runtime needs the ioctl code included in this patch to issue socket operations on the host machine. Change-Id: I687b31f375a846f0bab2debd9b9472605a4d2c7d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12123 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-29sim-se: create Proc out files in out dirSteve Reinhardt
Redirected output files from Process objects were being created in the current directory instead of in the output directory. Change-Id: Ieb6ab5556fbcc811f4f24910da247d4dcdbc71bd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12122 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-28arch, sim: Simplify the AuxVector type.Gabe Black
The AuxVector type has a bunch of accessors which just give access to the underlying variables through references. We might as well just make those members accessible directly. Also, the AuxVector doesn't need to handle endianness flips itself. We can tell the byteswap mechanism how to flip an AuxVector, and let it handle that for us. This gets rid of the entire .cc file which was complicated by trying to both hide the ISA specific endianness translations, and instantiate templated functions in a .cc. Change-Id: I433cd61e73e0b067b6d628fba31be4a4ec1c4cf0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18373 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-28mem: Remove the ISA specialized versions of port proxy's read/write.Gabe Black
These selected their behavior based on ifdefs and had to be disabled when on the NULL ISA. The versions which take an explicit endianness have been renamed to just read/write instead of readGtoH and writeHtoG since the direction of the translation is obvious from context. Change-Id: I6cfbfda6c4481962d442d3370534e50532d41814 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18372 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-28mem: Minimize the use of MemObject.Gabe Black
MemObject doesn't provide anything beyond its base ClockedObject any more, so this change removes it from most inheritance hierarchies. Occasionally MemObject is replaced with SimObject when I was fairly confident that the extra functionality of ClockedObject wasn't needed. Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-04-25sim-se: add a faux-filesystemDavid Hashe
This change introduces the concept of a faux-filesystem. The faux-filesystem creates a directory structure in m5out (or whatever output dir the user specifies) where system calls may be redirected. This is useful to avoid non-determinism when reading files with varying path names (e.g., variations from run-to-run if the simulation is scheduled on a cluster where paths may change). Also, this changeset allows circumventing host pseudofiles which have information specific to the host processor (such as cache hierarchy or processor information). Bypassing host pseudofiles can be useful when executing runtimes in the absence of an operating system kernel since runtimes may try to query standard files (i.e. /proc or /sys) which are not relevant to an application executing in syscall emulation mode. Change-Id: I90821b3b403168b904a662fa98b85def1628621c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12119 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-22sim-se: Enhance clone for X86KvmCPUAlexandru Dutu
This changeset enables clone to work with X86KvmCPU model, which will allow running multi-threaded applications at near hardware speeds. Even though the application is multi-threaded, the KvmCPU model uses one event queue, therefore, only one hardware thread will be used, through KVM, to simulate multiple application threads. Change-Id: I2b2a7b1edb1c56eeb9c4fa0553cd236029cd53f8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18268 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary. Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-19mem: Move bind() and unbind() into the Port class.Gabe Black
These are now pure virtual methods which more specialized port subclasses will need to implement. The SlavePort class implements them by ignoring them and then providing parallel functions for the MasterPort to call. The MasterPort's methods do basically what they did before, except now bind() uses dynamic cast to check if its peer is of the appropriate type and also to convert it into that type before connecting to it. Change-Id: I0948799bc954acaebf371e6b6612cee1d3023bc4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17038 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-19sim: Add a getPort function to SimObject.Gabe Black
This will retrieve a Port object from a given SimObject (which might not be a MemObject) no matter what flavor of Port it is. Change-Id: I636b85e9d4929a05a769e165849106bcb5f3e9c1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17037 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-15mem: Move the Port base class into sim.Gabe Black
The Port class is going to be officially used for more than just memory system connections. Change-Id: I493e721f99051865c5f0c06946a2303ff723c2af Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17036 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-12sim: Add size to array unserialization error messageDaniel R. Carvalho
Add both acquired and expected size information to array unserialization error message. Change-Id: Ic0a493c5a7860066eb992e9e91e7a4746b197579 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16542 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-19sim: Add a mechanism to exit the simulation loop immediately.Gabe Black
There are some cases, specifically when running systemc, that it's necessary to exit the simulation loop immediately rather than finishing running events scheduled for the current Tick. When running under sc_main, sc_stop and sc_pause return control to sc_main which can happen immediately. When running without sc_main, control needs to return to the python config script which needs to happen through a global exit event. Since sc_pause and sc_stop are supposed to stop simulation without necessarily letting all the events at the current time run, we need a way to schedule an exit event with a very high priority (rather than a very low priority). This change adds a new exitSimLoopNow function which does that, and adds a new constructor to the GlobalSimLoopExitEvent which uses that priority. Also, a couple of cruft functions from the sim events are removed. Change-Id: Icfbec17fb10f98084a75740acd839dbf4096fbb3 Reviewed-on: https://gem5-review.googlesource.com/c/16444 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
The importer in Python 3 doesn't like the way we import SimObjects from the global namespace. Convert the existing SimObject declarations to import from m5.objects. As a side-effect, this makes these files consistent with configuration files. Change-Id: I11153502b430822130722839e1fa767b82a027aa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15981 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-12python: Fix native module initialisation on Python 3Andreas Sandberg
The approach we currently use to register our native modules doesn't work on Python 3. Convert the code to use the Python inittab instead of the old ad-hoc method. Change-Id: I961f8a33993c621473732faeaab955a882769a4b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15979 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com>
2019-02-08kern,sim: implement FUTEX_WAKE_OPMoyang Wang
This patch implements FUTEX_WAKE_OP operation in the futex syscall. Below is its description: int futex(int *uaddr, int futex_op, int val, const struct timespec *timeout, int *uaddr2, int val3); This operation was added to support some user-space use cases where more than one futex must be handled at the same time. The most notable example is the implementation of pthread_cond_signal(3), which requires operations on two futexes, the one used to implement the mutex and the one used in the implementation of the wait queue associated with the condition variable. FUTEX_WAKE_OP allows such cases to be implemented without leading to high rates of contention and context switching. Reference: http://man7.org/linux/man-pages/man2/futex.2.html Change-Id: I215f3c2a7bdc6374e5dfe06ee721c76933a10f2d Reviewed-on: https://gem5-review.googlesource.com/c/9630 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-08sim, kern: support FUTEX_CMP_REQUEUEMoyang Wang
This patch supports FUTEX_CMP_REQUEUE operation. Below is its description from Linux man page: futex syscall: int futex(int *uaddr, int futex_op, int val, const struct timespec *timeout, int *uaddr2, int val3); This operation first checks whether the location uaddr still contains the value val3. If not, the operation fails with the error EAGAIN. Otherwise, the operation wakes up a maximum of val waiters that are waiting on the futex at uaddr. If there are more than val waiters, then the remaining waiters are removed from the wait queue of the source futex at uaddr and added to the wait queue of the target futex at uaddr2. The val2 argument specifies an upper limit on the number of waiters that are requeued to the futex at uaddr2. Reference: http://man7.org/linux/man-pages/man2/futex.2.html Change-Id: I6d2ebd19a935b656d19d8342f7ab450c0d2031f4 Reviewed-on: https://gem5-review.googlesource.com/c/9629 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-02-08sim: handle the case when there're not enough HW thread contextsTuan Ta
In SE mode, since there's no OS scheduler, the number of active SW threads is limited by the number of HW thread contexts. Previously, if there is no spare HW thread context, the simulator just fails and stops. Instead, this patch returns EAGAIN error code from a clone syscall if there's no available HW thread context. Then it's up to the simulated program to handle the error. Linux man page reference: http://man7.org/linux/man-pages/man2/clone.2.html http://man7.org/linux/man-pages/man2/fork.2.html Change-Id: Ib4e092433e49de4dde376c8cb81f7d3f7851cbc0 Reviewed-on: https://gem5-review.googlesource.com/c/9628 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-02-08sim,cpu: make exit_group halt all threads in a groupTuan Ta
When a thread calls exit_group, in addition to halting the thread itself, it needs to halt all other threads in its group (i.e., threads sharing the same thread group ID). This patch enables threads to do that. Change-Id: Ib2e158fb27cf98843f177a64a2d643b1bbc94d03 Reviewed-on: https://gem5-review.googlesource.com/c/9623 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-08sim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET opsTuan Ta
This patch adds support for two operations in futex system call: FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET. The two operations are used to selectively wake up a certain thread waiting on a futex variable. Basically each thread waiting on a futex variable is associated with a bitset that is checked when another thread tries to wake up all threads waiting on the futex variable. Change-Id: I2300e53b144d8fae226423fa2efb0238c1d93ef9 Reviewed-on: https://gem5-review.googlesource.com/c/9621 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-02-08cpu: fixed how O3 CPU executes an exit system callTuan Ta
When a thread executed an exit syscall in SE mode, the thread context was removed immediately in the same cycle, which left inflight squash operations and trap event incomplete. The problem happened when a new thread was assigned to the CPU later. The new thread started with some incomplete transactions of the previous thread (e.g., squashing). This problem could cause incorrect execution flow for the new thread (i.e., pc was not reset properly at the exit point), deadlock (i.e., some stage-to-stage signals were not reset) and incorrect rename map between logical and physical registers. This patch adds a new state called 'Halting' to the thread context and defers removing thread context from a CPU until a trap event initiated by an exit syscall execution is processed. This patch also makes sure that the removal of a thread context happens after all inflight transactions of the to-be-removed thread in the pipeline complete. Change-Id: If7ef1462fb8864e22b45371ee7ae67e2a5ad38b8 Reviewed-on: https://gem5-review.googlesource.com/c/8184 Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-07arch-riscv: Enable support for riscv 32-bit in SE mode.Austin Harris
This patch splits up the riscv SE mode support for 32 and 64-bit. A future patch will add support for decoding rv32 instructions. Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15355 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2019-02-06sim: added missed macro definition on MacOSAndrea Mondelli
A recent patch add the use of the macro: CMSG_ALIGN This macro is not very cross-platform, and needs to be defined according to the platform. This patch defines the missing macro on MacOS. Change-Id: I582f69e652dc060b4532358141179ad6d37eafc7 Reviewed-on: https://gem5-review.googlesource.com/c/16102 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-01-31sim: Prepare C++ side for Python 3Andreas Sandberg
Python 3 uses wide strings instead of ordinary strings for many APIs. Add the necessary conversions to comply with the new API. Change-Id: I6f45c9c532537d50d54b542f34eb8fd8cb375874 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15977 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector Extension (SVE), introduce the notion of a predicate register file. This changeset adds this feature across architectures and CPU models. Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13715 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-01-22sim-se add readv and modifies writevBrandon Potter
Change-Id: I6cbce4389d5697da34058dc910306394e48c6582 Reviewed-on: https://gem5-review.googlesource.com/c/12117 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-22sim-se: add ability to get/set sock metadataBrandon Potter
Add getsockopt, getsockname, setsockname, and getpeername system calls. Change-Id: Ifa1d9a95f15b4fb12859dbfd3c4bd248de2e3d32 Reviewed-on: https://gem5-review.googlesource.com/c/12116 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-22sim-se: add syscalls related to pollingBrandon Potter
Fix poll so that it will use the syscall retry capability instead of causing a blocking call. Add the accept and wait4 system calls. Add polling to read to remove deadlocks that occur in the event queue that are caused by blocking system calls. Modify the write system call to return an error number in case of error. Change-Id: I0b4091a2e41e4187ebf69d63e0088f988f37d5da Reviewed-on: https://gem5-review.googlesource.com/c/12115 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-22sim-se: add calls for network transmissionsBrandon Potter
Add recvfrom, sendto, recvmsg, and sendmsg system calls. Change-Id: I2eb50ea7823c8af57d99b3b8d443d2099418c06c Reviewed-on: https://gem5-review.googlesource.com/c/12114 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-22sim-se: add socket-based functionalityBrandon Potter
Add socket, socketpair, bind, list, connect and shutdown system calls. Change-Id: I635af3fca410f96fe28f8fe497e3d457a9dbc470 Reviewed-on: https://gem5-review.googlesource.com/c/12113 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-18base: Fix unitialized storageDaniel R. Carvalho
The bitunion is not being initialized on constructor to avoid performance overhead, and that generated a maybe-unitialized error when a sub-class was being copied before assigned in serialize's parseParam() in some compilers. This patch adds zero-initialization to the problematic variable to appease the compiler. Change-Id: I90fa6aa356b3e14ec25e3294b17ed10f429a9a38 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/15635 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-16cpu: dev: sim: gpu-compute: Banish some ISA specific register types.Gabe Black
These types are IntReg, FloatReg, FloatRegBits, and MiscReg. There are some remaining types, specifically the vector registers and the CCReg. I'm less familiar with these new types of registers, and so will look at getting rid of them at some later time. Change-Id: Ide8f76b15c531286f61427330053b44074b8ac9b Reviewed-on: https://gem5-review.googlesource.com/c/13624 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-10sim-se, arch-arm: Add support for getdents64Javier Setoain
Change-Id: Ib27950144d4c9802ffb842db98aec9e433ccbfc5 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15438 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-01-10sim-se: Refactor clone to avoid most ifdefsAndreas Sandberg
Some parts of clone are architecture dependent. In some cases, we are able to use architecture-specific helper functions or register aliases. However, there is still some architecture-specific that is protected by ifdefs in the common clone implementation. Move these architecture-specific bits to the architecture-specific OS class instead to avoid these ifdefs and make the code a bit more readable. Change-Id: Ia0903d738d0ba890863bddfa77e3b717db7f45de Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15435 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-01-10sim-se: Correctly calculate next PC in cloneAndreas Sandberg
The clone syscall doesn't propagate all state in the PCState object when calculating the return PC of a newly created process. Instead of creating a new PCState object from the next PC address, copy the old PC and advance it. Change-Id: Ice53831920bcb5d198865169ed2cca8d06e37cfe Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15417 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-01-10sim-se: Use CONFIG_CLONE_BACKWARDS for ArmAndreas Sandberg
Linxu on Arm users the CLONE_BACKWARDS argument order for the clone syscall. Change-Id: I48deb4f03140c9d4ef7a89e3e33813e76777f999 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15416 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-12-05arch-x86: Add sys/syscall.h to x86 process.cc/syscall_emul.ccTony Gutierrez
Change a66d12c guards the selection of getdents() in x86's process.cc file with SYS_getdents, however process.cc does not include the right header for SYS_getdents, which leads to x86 choosing the unimplemented call. This change adds sys/syscall.h to address the problem. This change also adds sys/syscall.hh to syscall_emu.cc, which only includes syscall.hh and may not be supported on all systems. Change-Id: If1adcf41e9e455de5f2827ba98c542fdcacdc22e Reviewed-on: https://gem5-review.googlesource.com/c/14775 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-12-04base, sim: Add missing destructorsNikos Nikoleris
Derived classes with virtual functions need to define a virtual destructor or a protected destructor otherwise calling the base class destructor has undefined behavior. This change adds a virtual distructor in the base class. Change-Id: I1c855aa56dff6585ff99b9147bdb4eb9729a0a53 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14815 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-11-27sim-se: only implement getdentsFunc on supported hostsCiro Santilli
The implementation of the getdents syscall relies on SYS_getdents, which is not available on all archs, because the getdents syscall has been superseded by getdents64, and does not exist on newer archs such as aarch64. This leads the build to break on aarch64 hosts with error: error: 'SYS_getdents' was not declared in this scope Change-Id: I8701fb5b61c0418b14a9463ef135a391a7f7a9ba Reviewed-on: https://gem5-review.googlesource.com/c/14596 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
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