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AgeCommit message (Expand)Author
2019-10-12arch,base: Separate the idea of a memory image and object file.Gabe Black
2019-10-10arch, base: Stop assuming object files have three segments.Gabe Black
2019-10-09base: Rename Section to Segment, and some of its members.Gabe Black
2019-10-03sim-se: Fix invalid delete of params on cloneJason Lowe-Power
2019-10-02sim: Mark System::getThreadContext method as constGiacomo Travaglini
2019-09-26sim: Convert power modelling framework to new-style statsAndreas Sandberg
2019-08-29stats: Add support for hierarchical statsAndreas Sandberg
2019-08-27sim: Add a << overload for the Port class which prints its name.Gabe Black
2019-08-27sim: Add a takeOverFrom method to the base Port class.Gabe Black
2019-08-27mem, sim, systemc: Reorganize Port and co.s bind, unbind slightly.Gabe Black
2019-08-13sim: Add a hook Clocked objects can implement for frequency changes.Gabe Black
2019-08-13sim: Clean up some mild style bugs in clocked_object.hh.Gabe Black
2019-08-12sim-se: rename Process::setpgid memberBrandon Potter
2019-08-09sim-se: minor refactor for ProcessParams::createBrandon Potter
2019-08-09sim-se: remove unused parameterBrandon Potter
2019-08-06sim-se: add new getpgrp system callBrandon Potter
2019-08-06sim-se: adding pipe2 syscallMatthew Sinclair
2019-08-02sim-se: small refactor on pipe syscallBrandon Potter
2019-08-01sim-se: small performance optimizationBrandon Potter
2019-08-01sim-se: fstat64 bugfixBrandon Potter
2019-08-01sim-se: add new option to getrlimit syscallBrandon Potter
2019-07-18sim: Add getter to fault virtual addressGabor Dozsa
2019-05-30arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.Gabe Black
2019-05-30cpu, sim: Return PortProxy &s from all the proxy accessors.Gabe Black
2019-05-30arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to PortProxy &s.Gabe Black
2019-05-30arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.Gabe Black
2019-05-29sim-se: add a release parameter to Process.pyCiro Santilli
2019-05-29arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.Gabe Black
2019-05-21sim-se: change syscall function signatureBrandon Potter
2019-05-21sim-se: remove /sys from special pathsTony Gutierrez
2019-05-20sim: Make the Process create function use the object loader mechanism.Gabe Black
2019-05-18arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.Gabe Black
2019-05-06sim-se: correct statfs inclusion on !linux hostAndrea Mondelli
2019-05-03sim-se: fix a few bugs/warns from GCC 6Joe Gross
2019-05-03sim-se: add eventfd system callBrandon Potter
2019-04-30sim-se: use DPRINTF_SYSCALL for ioctl/wait4Alexandru Dutu
2019-04-30sim-se: bugfix for 54c77aa055eBrandon Potter
2019-04-30arch: cpu: Track kernel stats using the base ISA agnostic type.Gabe Black
2019-04-30sim-se: add socket ioctlsBrandon Potter
2019-04-29sim-se: create Proc out files in out dirSteve Reinhardt
2019-04-28arch, sim: Simplify the AuxVector type.Gabe Black
2019-04-28mem: Remove the ISA specialized versions of port proxy's read/write.Gabe Black
2019-04-28mem: Minimize the use of MemObject.Gabe Black
2019-04-25sim-se: add a faux-filesystemDavid Hashe
2019-04-22sim-se: Enhance clone for X86KvmCPUAlexandru Dutu
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
2019-03-19mem: Move bind() and unbind() into the Port class.Gabe Black
2019-03-19sim: Add a getPort function to SimObject.Gabe Black
2019-03-15mem: Move the Port base class into sim.Gabe Black
2019-03-12sim: Add size to array unserialization error messageDaniel R. Carvalho
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