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path: root/src/sim
AgeCommit message (Expand)Author
2019-05-30arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.Gabe Black
2019-05-30cpu, sim: Return PortProxy &s from all the proxy accessors.Gabe Black
2019-05-30arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to PortProxy &s.Gabe Black
2019-05-30arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.Gabe Black
2019-05-29sim-se: add a release parameter to Process.pyCiro Santilli
2019-05-29arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.Gabe Black
2019-05-21sim-se: change syscall function signatureBrandon Potter
2019-05-21sim-se: remove /sys from special pathsTony Gutierrez
2019-05-20sim: Make the Process create function use the object loader mechanism.Gabe Black
2019-05-18arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.Gabe Black
2019-05-06sim-se: correct statfs inclusion on !linux hostAndrea Mondelli
2019-05-03sim-se: fix a few bugs/warns from GCC 6Joe Gross
2019-05-03sim-se: add eventfd system callBrandon Potter
2019-04-30sim-se: use DPRINTF_SYSCALL for ioctl/wait4Alexandru Dutu
2019-04-30sim-se: bugfix for 54c77aa055eBrandon Potter
2019-04-30arch: cpu: Track kernel stats using the base ISA agnostic type.Gabe Black
2019-04-30sim-se: add socket ioctlsBrandon Potter
2019-04-29sim-se: create Proc out files in out dirSteve Reinhardt
2019-04-28arch, sim: Simplify the AuxVector type.Gabe Black
2019-04-28mem: Remove the ISA specialized versions of port proxy's read/write.Gabe Black
2019-04-28mem: Minimize the use of MemObject.Gabe Black
2019-04-25sim-se: add a faux-filesystemDavid Hashe
2019-04-22sim-se: Enhance clone for X86KvmCPUAlexandru Dutu
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
2019-03-19mem: Move bind() and unbind() into the Port class.Gabe Black
2019-03-19sim: Add a getPort function to SimObject.Gabe Black
2019-03-15mem: Move the Port base class into sim.Gabe Black
2019-03-12sim: Add size to array unserialization error messageDaniel R. Carvalho
2019-02-19sim: Add a mechanism to exit the simulation loop immediately.Gabe Black
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
2019-02-12python: Fix native module initialisation on Python 3Andreas Sandberg
2019-02-08kern,sim: implement FUTEX_WAKE_OPMoyang Wang
2019-02-08sim, kern: support FUTEX_CMP_REQUEUEMoyang Wang
2019-02-08sim: handle the case when there're not enough HW thread contextsTuan Ta
2019-02-08sim,cpu: make exit_group halt all threads in a groupTuan Ta
2019-02-08sim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET opsTuan Ta
2019-02-08cpu: fixed how O3 CPU executes an exit system callTuan Ta
2019-02-07arch-riscv: Enable support for riscv 32-bit in SE mode.Austin Harris
2019-02-06sim: added missed macro definition on MacOSAndrea Mondelli
2019-01-31sim: Prepare C++ side for Python 3Andreas Sandberg
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
2019-01-22sim-se add readv and modifies writevBrandon Potter
2019-01-22sim-se: add ability to get/set sock metadataBrandon Potter
2019-01-22sim-se: add syscalls related to pollingBrandon Potter
2019-01-22sim-se: add calls for network transmissionsBrandon Potter
2019-01-22sim-se: add socket-based functionalityBrandon Potter
2019-01-18base: Fix unitialized storageDaniel R. Carvalho
2019-01-16cpu: dev: sim: gpu-compute: Banish some ISA specific register types.Gabe Black
2019-01-10sim-se, arch-arm: Add support for getdents64Javier Setoain
2019-01-10sim-se: Refactor clone to avoid most ifdefsAndreas Sandberg
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