Age | Commit message (Expand) | Author |
2019-04-28 | mem: Minimize the use of MemObject. | Gabe Black |
2019-04-25 | sim-se: add a faux-filesystem | David Hashe |
2019-04-22 | sim-se: Enhance clone for X86KvmCPU | Alexandru Dutu |
2019-03-19 | arch, cpu, dev, gpu, mem, sim, python: start using getPort. | Gabe Black |
2019-03-19 | mem: Move bind() and unbind() into the Port class. | Gabe Black |
2019-03-19 | sim: Add a getPort function to SimObject. | Gabe Black |
2019-03-15 | mem: Move the Port base class into sim. | Gabe Black |
2019-03-12 | sim: Add size to array unserialization error message | Daniel R. Carvalho |
2019-02-19 | sim: Add a mechanism to exit the simulation loop immediately. | Gabe Black |
2019-02-12 | python: Don't assume SimObjects live in the global namespace | Andreas Sandberg |
2019-02-12 | python: Fix native module initialisation on Python 3 | Andreas Sandberg |
2019-02-08 | kern,sim: implement FUTEX_WAKE_OP | Moyang Wang |
2019-02-08 | sim, kern: support FUTEX_CMP_REQUEUE | Moyang Wang |
2019-02-08 | sim: handle the case when there're not enough HW thread contexts | Tuan Ta |
2019-02-08 | sim,cpu: make exit_group halt all threads in a group | Tuan Ta |
2019-02-08 | sim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET ops | Tuan Ta |
2019-02-08 | cpu: fixed how O3 CPU executes an exit system call | Tuan Ta |
2019-02-07 | arch-riscv: Enable support for riscv 32-bit in SE mode. | Austin Harris |
2019-02-06 | sim: added missed macro definition on MacOS | Andrea Mondelli |
2019-01-31 | sim: Prepare C++ side for Python 3 | Andreas Sandberg |
2019-01-30 | arch,cpu: Add vector predicate registers | Giacomo Gabrielli |
2019-01-22 | sim-se add readv and modifies writev | Brandon Potter |
2019-01-22 | sim-se: add ability to get/set sock metadata | Brandon Potter |
2019-01-22 | sim-se: add syscalls related to polling | Brandon Potter |
2019-01-22 | sim-se: add calls for network transmissions | Brandon Potter |
2019-01-22 | sim-se: add socket-based functionality | Brandon Potter |
2019-01-18 | base: Fix unitialized storage | Daniel R. Carvalho |
2019-01-16 | cpu: dev: sim: gpu-compute: Banish some ISA specific register types. | Gabe Black |
2019-01-10 | sim-se, arch-arm: Add support for getdents64 | Javier Setoain |
2019-01-10 | sim-se: Refactor clone to avoid most ifdefs | Andreas Sandberg |
2019-01-10 | sim-se: Correctly calculate next PC in clone | Andreas Sandberg |
2019-01-10 | sim-se: Use CONFIG_CLONE_BACKWARDS for Arm | Andreas Sandberg |
2018-12-05 | arch-x86: Add sys/syscall.h to x86 process.cc/syscall_emul.cc | Tony Gutierrez |
2018-12-04 | base, sim: Add missing destructors | Nikos Nikoleris |
2018-11-27 | sim-se: only implement getdentsFunc on supported hosts | Ciro Santilli |
2018-11-20 | sim: Deschedule existing events when destructing an event queue. | Gabe Black |
2018-11-14 | sim: Move BitUnion overloading to show/parseParams | Giacomo Travaglini |
2018-11-14 | sim: Move paramIn/Out definition to header file | Giacomo Travaglini |
2018-11-12 | sim: Push the global frequency management code into C++. | Gabe Black |
2018-10-30 | syscall_emul: fix openat when directory does not end in "/" | Ciro Santilli |
2018-10-01 | sim: Extend (UN)SERIALIZE_ARRAY to BitUnions | Giacomo Travaglini |
2018-09-19 | syscall_emul: implement dir-related syscalls | Brandon Potter |
2018-09-19 | syscall_emul: refactor FDEntry and children classes | Brandon Potter |
2018-09-19 | syscall_emul: style changes and FDArray refactor | Brandon Potter |
2018-09-19 | syscall_emul: expand AuxVector class | Brandon Potter |
2018-09-14 | power: Add a clock_period variable to power expressions | Sherif Elhabbal |
2018-09-11 | base: Correct a small typo in sim/core.(hh|cc). | Gabe Black |
2018-09-07 | sim: Add System method for MasterID lookup | Giacomo Travaglini |
2018-06-25 | syscall_emul: adding symlink system call | Matt Sinclair |
2018-06-25 | syscall_emul: adding link system call | Matt Sinclair |